H03M13/155

Communication method and apparatus using segmented bit sequences

A communication method is provided, including: obtaining a to-be-segmented first bit sequence, where a quantity of bits in the first bit sequence is B, and a quantity of bits that can be carried by a physical resource corresponding to the first bit sequence is N.sub.1; determining, based on N.sub.1 and a parameter L, a quantity C of bit sequences obtained by segmenting the first bit sequence, where a value of L is equal to (B+B.sub.1)/R.sub.min,K.sub.max, R.sub.min,K.sub.max is a minimum bit rate corresponding to an available maximum code block length K.sub.max, and B.sub.1 is an integer greater than or equal to 0; and segmenting the first bit sequence into C segmented bit sequences. Based on the method, a proper code block segmentation scheme can be provided.

METHOD AND APPARATUS FOR PROVIDING A JOINT ERROR CORRECTION CODE FOR A COMBINED DATA FRAME COMPRISING FIRST DATA OF A FIRST DATA CHANNEL AND SECOND DATA OF A SECOND DATA CHANNEL AND SENSOR SYSTEM

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

Method and apparatus for providing a joint error correction code for a combined data frame comprising first data of a first data channel and second data of a second data channel and sensor system

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

Method and apparatus for transmitting and receiving signal by using polar coding

Disclosed are: a communication method for merging, with IoT technology, a 5G communication system for supporting a data transmission rate higher than that of a 4G system; and a system thereof. The present disclosure can be applied to intelligent services (for example, smart home, smart building, smart city, smart car or connected car, healthcare, digital education, retail, security and safety related services, and the like) on the basis of a 5G communication technology and an IoT-related technology. A method by which a transmitter in a communication system transmits signals, according to one embodiment of the present specification, comprises the steps of: determining depth information for generating a mother code size and a parity bit; applying a polar code sequence corresponding to an information bit; generating, on the basis of the mother code size and the depth information, a codeword including a parity bit associated with at least two bits among a plurality of bits to which the polar code sequence is applied; and transmitting the generated codeword.

Memory system with super chip-kill recovery and method of operating such memory system

Devices and methods that generate code on chip-kill parity in which the code is generated and shortened using variable node degree information for improved decoding of data. In one aspect, memory controller comprises an encoder configured to construct a first code of D data bits and P parity bits, determine the number of distinct variable degree nodes L and the number of data bits of each of the variable degree nodes in the first code, and construct a second code that is shorter than the first code based on the determined number of variable degree nodes and the number of data bits of each of the variable degree nodes in the first code.

Low-density parity-check code scaling method

A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.

Generating and using invertible, shortened Bose-Chaudhuri-Hocquenghem codewords
10855314 · 2020-12-01 · ·

A computer-implemented method for using invertible, shortened codewords is described. The method includes receiving a request to store user data bits in a set of memory devices; expanding the user data bits and an inversion bit to bit locations of a codeword template, wherein the expanding forms expanded inversion and user data bits that collectively include additional bits to represent the user data bits and the inversion bit; generating parity bits for the expanded inversion and user data bits to form a shortened codeword, wherein the shortened codeword comprises the expanded inversion and user data bits, and the parity bits; compressing the shortened codeword to form a compressed shortened codeword; and storing the compressed shortened codeword in the set of memory devices.

RATE MATCHING IN POLAR CODES
20200373945 · 2020-11-26 · ·

A communication apparatus includes: an encoder that encodes an input vector to output a codeword of polar code; a memory that stores a reliability-ordered sequence of indices of the input vector and a set of indices for rate-matching; a controller that is configured to: select a frozen set of indices based on at least one of a universal rate-matching scheme and the reliability-ordered sequence stored in the memory such that the reliability-ordered sequence is generated without considering the rate-matching scheme; construct the input vector by setting the frozen set to a frozen bit and a non-frozen set to information bits; and skip codebits of the codeword outputted by the encoder from transmission, the codebits corresponding respectively to the set of indices for rate-matching.

METHODS AND APPARATUS FOR CRC CONCATENATED POLAR ENCODING

Certain aspects of the present disclosure generally relate to techniques for encoding and decoding bits of information using cyclic redundancy check (CRC) concatenated polar encoding and decoding. The CRC concatenated polar encoding techniques may avoid transmission of dummy bits. A method generally includes obtaining the bits of information to be transmitted. The method includes performing CRC outer encoding of the bits of information using an even-weighted generator polynomial to produce CRC encoded bits. The method includes performing polar inner encoding of the CRC encoded bits to generate a codeword. The method includes discarding a first code bit at a beginning of the codeword. The shortened codeword is transmitted over a wireless medium. In another method, bit-level scrambling is performed on the CRC encoded bits before the polar encoding to avoid generating a dummy bit. In another method, only odd-weighted generator polynomials are selected to avoid generating the dummy bit.

Method for dividing transport block of LDPC code and apparatus therefor

Disclosed are a method for dividing a transport block of a low density parity check (LDPC) code and an apparatus therefor. A method for dividing a transport block of an LDPC code according to the present disclosure can improve the performance of the LDPC code by dividing the transport block using a minimum number of code blocks. In addition, it is possible to minimize shortening bits by making the size of some of the code blocks smaller than the size of the other code blocks. Further, it is possible to prevent performance degradation due to a minimum size code block by minimizing the number of the code blocks and performing shortening on a large size code block.