Disclosed are a method for dividing a carrying block of a Low Density Parity Check (LDPC) code and an apparatus therefor. The method for dividing a LDPC code of the present disclosure can obtain a high throughput by using a limited size of shifting network. Moreover, it is possible to prevent degradation in performance due to a minimum size of code block by performing shortening for a large size of code block while minimizing the number of code blocks. Furthermore, in selection of a minimum size of code block, since a minimum size of code block is selected on the basis of shortening for a relatively large size of code block, it is possible to increase the size of the minimum size of code block.

Certain aspects of the present disclosure generally relate to wireless communications and, more particularly, to methods and apparatus for rate-matching a stream of bits encoded using polar codes. An exemplary method generally includes encoding K information bits using a polar code with a mother code length, N, to generate a stream of encoded bits storing a portion of the encoded bits in a circular buffer of size N reordering P blocks of the circular buffer according to row weights of a Hadamard matrix J interlacing the encoded bits of the blocks having a same row weight selecting, based on the row weights, a subset of the encoded bits in the blocks to modify modifying the selected subset of the encoded bits and transmitting the encoded bits in the P blocks, subsequent to modifying the selected subset of the encoded bits, via transmission resources.

Disclosed are a method for dividing a carrying block of a Low Density Parity Check (LDPC) code and an apparatus therefor. The method for dividing a LDPC code of the present disclosure can obtain a high throughput by using a limited size of shifting network. Moreover, it is possible to prevent degradation in performance due to a minimum size of code block by performing shortening for a large size of code block while minimizing the number of code blocks. Furthermore, in selection of a minimum size of code block, since a minimum size of code block is selected on the basis of shortening for a relatively large size of code block, it is possible to increase the size of the minimum size of code block.

A memory controller according to an embodiment includes a memory interface that reads out a received word from a non-volatile memory and a decoder that performs bounded distance decoding for the read received word. The decoder sets r.sub.m (r.sub.m is a natural number equal to or larger than 1) symbols of a plurality of symbols constituting the received word, as options of symbol positions at each of which an error is assumed, generates a test pattern in which m (m is a natural number equal to or larger than 1 and equal to or smaller than the r.sub.m) symbols of the r.sub.m symbols are objects of rewriting, generates test hard-decision values by rewriting each of hard-decision values of the m symbols that are objects of rewriting in the test pattern, among the symbols, and performs bounded distance decoding for the test hard-decision values.

A method and associated apparatus is disclosed for processing data by means of an error code, wherein the error code has an H-matrix with n columns and m rows, wherein the columns of the H-matrix are different, wherein component-by-component XOR sums of adjacent columns of the H-matrix are different from one another and from all columns of the H-matrix and wherein component-by-component XOR sums of nonadjacent columns of the H-matrix are different from all columns of the H-matrix and from all component-by-component XOR sums of adjacent columns of the H-matrix.

The present disclosure relates to methods and systems for decoding a low density parity check (LDPC) encoded codeword. The methods may include receiving a codeword over a data channel. The codeword may be encoded with a preset number of data bits having one or more shortened data bits. The methods may also include obtaining a parity check matrix that defines relationships between a plurality of variable nodes and a plurality of check nodes. The methods may further include decoding the codeword by iteratively estimating values with respect to the codeword at the plurality of variable nodes and the plurality of check nodes. During each iteration, a same part of the plurality of variable nodes related to one or more shortened data bits are skipped from estimation.

A low-density parity-check code scaling method is disclosed. The method includes following steps: obtaining the original low-density parity-check matrix; forming the permutation matrices with the random row shift or the random column shift to the identity matrix; replacing the component codes by the permutation matrices and the all-zero matrix to form the extended low-density parity-check matrix; adjusting the code length and the code rate to form the global coupled low-density parity-check matrix; and outputting the global coupled low-density parity-check code.

A data transmission method, a chip, a transceiver, and a computer readable storage medium are provided. The method includes: obtaining K information bits; determining to-be-encoded bits, where the to-be-encoded bits include (K+P) bits, the (K+P) bits include the K information bits and P check bits, the K information bits correspond to K polarization channels, the P check bits include T first-type check bits, all the T first-type check bits are PC bits, and reliability of a polarization channel corresponding to each of the T first-type check bits is greater than a minimum value of reliability of the K polarization channels; and performing polar coding on the to-be-encoded bits to obtain encoded bits, where the (K+P) bits are in a one-to-one correspondence with (K+P) rows in a generator matrix of the encoded bits, a maximum row weight corresponding to the T first-type check bits is less than or equal to W.sub.2.

Disclosed are a method for dividing a transport block of a low density parity check (LDPC) code and an apparatus therefor. A method for dividing a transport block of an LDPC code according to the present disclosure can improve the performance of the LDPC code by dividing the transport block using a minimum number of code blocks. In addition, it is possible to minimize shortening bits by making the size of some of the code blocks smaller than the size of the other code blocks. Further, it is possible to prevent performance degradation due to a minimum size code block by minimizing the number of the code blocks and performing shortening on a large size code block.

The present disclosure relates to methods and systems for decoding a low density parity check (LDPC) encoded codeword. The methods may include receiving a codeword over a data channel. The codeword may be encoded with a preset number of data bits having one or more shortened data bits. The methods may also include obtaining a parity check matrix that defines relationships between a plurality of variable nodes and a plurality of check nodes. The methods may further include decoding the codeword by iteratively estimating values with respect to the codeword at the plurality of variable nodes and the plurality of check nodes. During each iteration, a same part of the plurality of variable nodes related to one or more shortened data bits are skipped from estimation.