A method for Bose-Chaudhuri-Hocquenghem (BCH) soft error decoding includes receiving a codeword x, wherein the received codeword x has τ=t+r errors for some r≥1; computing a minimal monotone basis {λ.sub.i(x)}.sub.1≤i≤r+1.Math.F[x] of an affine space V={λ(x)ϵF[x]: λ(x).Math.S(x)=λ′(x) (mod x.sup.2t), λ(0)=1, deg(λ(x)≤t+r}, wherein λ(x) is an error locator polynomial and S(x) is a syndrome; computing a matrix A≡(λ.sub.jβ.sub.i)).sub.iϵ[W],jϵ[r+1], wherein W={β.sub.i, . . . , β.sub.W} is a set of weak bits in x; constructing a submatrix of r+1 rows from sub matrices of r+1 rows of the subsets of A such that the last column is a linear combination of the other columns; forming a candidate error locating polynomial using coefficients of the minimal monotone basis that result from the constructed submatrix; performing a fast Chien search to verify the candidate error locating polynomial; and flipping channel hard decision at error locations found in the candidate error locating polynomial.

A device for decoding a generalized concatenated code (GCC) codeword includes: a buffer; and at least one processor configured to: obtain the GCC codeword, calculate a plurality of inner syndromes based on a plurality of frames; calculate a plurality of sets of delta syndromes based on the frames; determine a plurality of outer syndromes based on the sets of delta syndromes; store the inner syndromes and the outer syndromes in a buffer; perform inner decoding on the frames based on the inner syndromes stored in the buffer; update at least one outer syndrome stored in the buffer based on a result of the inner decoding; perform outer decoding on the frames based on the updated at least one outer syndrome; and obtain decoded information bits corresponding to the GCC codeword based on a result of the inner decoding and the result of the outer decoding.

A quantum computing device comprises a surface code lattice that includes/logical qubits, where/is a positive integer. The surface code lattice is partitioned into two or more regions based on lattice geometry. A compression engine is coupled to each logical qubit of the/logical qubits. Each compression engine is configured to compress syndrome data generated by the surface code lattice using a geometry-based compression scheme. A decompression engine is coupled to each compression engine. Each decompression engine is configured to receive compressed syndrome data, decompress the received compressed syndrome data, and route the decompressed syndrome data to a decoder block.

Disclosed are various approaches for a controller that can generate and use non-stationary polar codes for encoding and decoding information. In one example, a method includes performing, by an encoder of the controller, a linear operation on at least one vector of information to be stored in a memory. The linear operation includes generating a polar encoded representation from the at least one vector of information. The linear operation also includes generating an output using at least one permutation that is based on a statistical characterization analysis of channels of the memory and a channel dependent permutation that is applied to the polar encoded representation. In some aspects, the statistical characterization analysis includes a respective reliability level of each one of the plurality of channels, and the channel dependent permutation includes an ordered permutation that orders the channels according to their respective reliability level.

A semiconductor system includes a controller configured to, in a write operation, output write data and a write error code through at least any one of input/output lines, and in a read operation, receive read data and a read error code through at least any one of the input/output lines and detect a failure of the input/output lines depending on whether the read data is error-corrected; and a semiconductor device configured to, in the write operation, correct an error of the write data based on the write error code, store the error-corrected write data and store the write error code, and in the read operation, correct an error of the write data based on the write error code stored in the write operation, output the error-corrected write data as the read data, and output the write error code stored in the write operation, as the read error code.

A device includes an arbiter circuit configured to receive a first request for a resource. The first request is associated with a first credit cost. The arbiter circuit is further configured to receive a second request for the resource. The second request is associated with a second credit cost. The arbiter circuit is further configured to select the first request for the resource as an arbitration winner. The arbiter circuit is further configured to decrement a number of available credits associated with the resource by the first credit cost. The arbiter circuit is further configured to, in response to the number of available credits associated with the resource falling to a lower credit threshold, wait until the number of available credits associated with the resource reaches an upper credit threshold to select an additional arbitration winner for the resource.

A cyclic redundancy check, CRC, decoder circuit having a K-bit input bit sequence, s, comprising information bits and CRC bits; and at least one processor (P) configured to perform a CRC decode computation and configured to: use an inverse of a predefined CRC generator polynomial that encoded the K-bit input bit sequence, s, to produce a data set; compute a CRC syndrome from the data set; and determine whether the CRC syndrome contains any one-valued bits indicative of a CRC error. An LUT stores one or more rows of a CRC generator matrix (G) generated from the inverse of the predefined CRC generator polynomial. A set of mod(−K,P) zero-valued filler bits are appended to an end of the K-bit input bit sequence, wherein an order of the rows in the CRC generator matrix (G) is reversed and aligned with the input bits of the input stream.

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

A computer-implemented method of processing a query vector and a data vector), comprising: generating a set of masks and a first set of multiple signatures and a second set of multiple signatures by applying the set of masks to the query vector and the data vector, respectively, and generating candidate pairs, of a first signature and a second signature, by identifying matches of a first signature and a second signature. The set of masks comprises a configuration of the elements that is a Hadamard code; a permutation of a Hadamard code; or a code that deviates from a Hadamard code or a permutation of a Hadamard code in less than 40% of its elements.

A memory system includes a memory controller including: a memory core configured to store data and an error correction code corresponding to the data; a syndrome generator configured to generate a first syndrome by substituting the data and the error correction code, read from the memory core, into a first check matrix, and generate a second syndrome by substituting the data and the error correction code, read from the memory core, into a second check matrix; and an error correction unit configured to correct an error of the read data and error correction code by using the first syndrome and the second syndrome, wherein constituents having values of ‘1’ in the first check matrix have values of ‘1’ also in the second check matrix.