An electronic device includes an error correction circuit configured to detect an error included in internal data, to generate a failure detection signal during a read operation, and to correct the error included in the internal data during a refresh operation, and a core circuit configured to store an address signal for activating a word line in which the internal data including the error is stored through as a failure address signal when the failure detection signal is input to the core circuit, and store the error-corrected internal data in the core circuit through a word line activated by the failure address signal during the refresh operation.

Novel and useful quantum structures having a continuous well with control gates that control a local depletion region to form quantum dots. Local depleted well tunneling is used to control quantum operations to implement quantum computing circuits. Qubits are realized by modulating gate potential to control tunneling through local depleted region between two or more sections of the well. Complex structures with a higher number of qdots per continuous well and a larger number of wells are fabricated. Both planar and 3D FinFET semiconductor processes are used to build well to gate and well to well tunneling quantum structures. Combining a number of elementary quantum structure, a quantum computing machine is realized. An interface device provides an interface between classic circuitry and quantum circuitry by permitting tunneling of a single quantum particle from the classic side to the quantum side of the device. Detection interface devices detect the presence or absence of a particle destructively or nondestructively.

A decoding device receives transmission data obtained by scrambling according to a polynomial x.sup.a+x.sup.b+1 where a and b are each an integer, a>b, and a≠2b. The decoding device includes a receiving unit, an error detecting unit, and a correcting unit. The receiving unit receives data obtained by scrambling transmission data in a block of 2.sup.N or less bits and an (N+3)-bit error correcting code. The (N+3)-bit error correcting code is calculated according to an (N+3)-degree cyclic code generator polynomial that is preset to generate 2.sup.N or more types of consecutive syndromes indicating bit error locations. The error detecting unit calculates, from (2.sup.(N+3)−1) types of syndromes and on the basis of a table, a bit error location in descrambled data obtained by descrambling the received data. The correcting unit corrects the descrambled data at the error location calculated by the error detecting unit.

An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a memory configured to store a line of data and an error correcting code (ECC) syndrome associated with the line of data, where the ECC syndrome is calculated based on the line of data and the ECC syndrome is a first type ECC. The cache subsystem also includes a controller configured to, in response to a request from a master configured to implement a second type ECC, the request being directed to the line of data, transform the first type ECC syndrome for the line of data to a second type ECC syndrome send a response to the master. The response includes the line of data and the second type ECC syndrome associated with the line of data.

A decoding device receives transmission data obtained by scrambling according to a polynomial x.sup.a+x.sup.b+1 where a and b are each an integer, a>b, and a≠2b. The decoding device includes a receiving unit, an error detecting unit, and a correcting unit. The receiving unit receives data obtained by performing scrambling for a block in which an error correcting code has been added to the transmission data of (n−8) bits where n<a. The error detecting unit calculates, on the basis of a table, an error location in descrambled data obtained by descrambling the received data. The correcting unit corrects the descrambled data at the error location calculated by the error detecting unit.

A syndrome calculation circuit receives input data r(x) including data and a parity bit and having a code length n of (2.sup.m-1) bits at maximum which is represented by a Galois field GF(2.sup.m), and performs syndrome calculation so as to meet

s≡α.sup.i+α.sup.j

z≡(α.sup.i+β).sup.−1+β.sup.−1+(α.sup.j+β).sup.−1+β.sup.1   (A)

thereby calculating syndromes s and z. An error position polynomial coefficient calculation circuit calculates the coefficient of an error position polynomial to obtain s×z by multiplying s and z by one multiplier. After that, 2-bit error data positions i and j are specified. Errors at the error data positions i and j of the input data are corrected.

A quantum-state-refresh module of a memory system is configured to detect an error in an entangled qubit state stored therein by performing a redundant measurement of syndrome values corresponding to a quantum stabilizer code, with the redundant measurement being based on a block error-correction code. The quantum-state-refresh module includes a plurality of measurement sub-modules, each configured to measure a respective syndrome value or a respective parity value corresponding to the entangled qubit state. The total number of the measurement sub-modules is smaller than the codeword length of the block error-correction code, and the initial approximation of the punctured syndrome values is replaced in the decoding process by erasure values. With the block error-correction code appropriately constructed for the use of erasure values, the quantum-state-refresh module is advantageously capable of providing reliable error detection with fewer quantum gates than that used for the full-length measurement of the codeword.

The disclosure relates to a pre-5.sup.th-generation (5G) or 5G communication system to be provided for supporting higher data rates beyond 4th-generation (4G) communication system, such as a long-term evolution (LTE). A method of a receiving device in a communication system is provided. The method includes receiving a signal, and decoding the received signal based on a polar decoding scheme which is based on a successive cancellation (SC) scheme to estimate an information sequence, wherein, in the polar decoding scheme, a second number of parity bits among a first number of parity bits of an outer code included in an input bit sequence to a polar encoder are used in an error detection operation, and a third number of parity bits among the first number of parity bits are used in an error correction operation.

Methods, systems, and apparatuses include receiving a codeword stored in a memory device. The codeword has bits from defective bit locations and non-defective bit locations. A syndrome of a current copy of the codeword is determined. Channel information for non-defective bit locations is determined using the current copy of the codeword and the received codeword from the memory device. Energy function values are determined for bits of the codeword using the syndrome of the current copy. Determining the energy function values includes using the channel information for bits in non-defective bit locations and omitting channel information for bits in defective bit locations. One or more bits of the codeword are flipped in response to the energy function values for the one or more bits satisfying a bit flipping criterion. A corrected codeword that results from the flipping of the bits is returned.

Processing of a bit sequence is proposed, wherein (i) a first partial error syndrome s.sub.1 of an error syndrome and a second partial error syndrome s.sub.2 of the error syndrome are determined for the bit sequence, (ii) a first comparison value is determined on the basis of a bit position and the first partial error syndrome, (iii) a second comparison value is determined on the basis of the bit position and the second partial error syndrome, and (iv) the bit position is corrected should a comparison of the first comparison value with the second comparison value assume a specified value and otherwise the bit position is not corrected.