An RFID circuit and to a demodulator for an RFID circuit, the demodulator including an input and at least one output, a clock extractor connected to the input, a comparator connected to at least one output, a finite impulse response FIR filter arrangement connected to the input and connected to the comparator.

Disclosed is receiver for a noise limited system. A front-end circuit amplifies and band-limits an incoming signal. The amplification increases the signal swing but introduces both thermal and flicker noise. A low-pass band limitation reduces the thermal noise component present at frequencies above what is necessary for correctly receiving the transmitted symbols. This band limited signal is provided to the integrator circuit. The output of the integrator is equalized to reduce the effects of inter-symbol interference and then sampled. The samples are used to apply low frequency equalization (i.e., in response to long and/or unbalanced strings of symbols) to mitigate the effects of DC wander caused by mismatches between the number of symbols of each kind being received.

Methods and systems of performing feed forward equalization (FFE) on data streams are described. A circuitry may generate staggered data streams from data streams of an input signal. The staggered data streams may include data in staggered unit intervals. The circuitry may include a plurality of segments. A segment may define a specific unit interval to carve the staggered data streams into one unit interval pulses positioned at the specific unit interval. The specific unit interval to carve the staggered data streams may indicate an assignment of the segment as one of a FFE pre tap, a FFE main tap, and a FFE post tap. The plurality of segments may be assigned to different FFE taps based on different clock signal selection defining different unit intervals to perform the carving. The plurality of segments may output respective one unit interval pulses to reproduce the input signal.

According to one embodiment, there is provided a semiconductor integrated circuit including a first equalizer and a clock reproduction circuit. The first equalizer boosts a data signal. The clock reproduction circuit extracts from the boosted data signal information of a pair consisting of a rise edge and a fall edge which are temporarily separated from each other by N or more times (N is an integer of two or higher) as much as a clock cycle, performs a phase adjustment based on the information about the pair of the rise edge and the fall edge, and reproduces a clock.

Systems and methods are disclosed for improving data channel design by applying transform domain analytics to more reliably extract user data from a signal. In certain embodiments, an apparatus may comprise a channel circuit configured to receive an analog signal at an input of the channel circuit, and sample the analog signal to obtain a set of signal samples. The channel circuit may further apply a filter configured to perform transform domain analysis to the set of signal samples to generate a first subset of samples, the first subset including fewer transitions and having a higher signal to noise ratio (SNR) than the set of signal samples. The channel circuit may detect first bit transform domain representation values from the first subset, and determine channel bit values encoded in the analog signal based on the set of signal samples and using the first bit transform domain representation values detected from the first subset as side information.

A continuous time linear equalization (CTLE) circuit is disclosed. The CTLE circuit includes an input port, an output port, a first differential transistor pair coupled to the input port and the output port and a second differential transistor pair. The CTLE circuit further includes a first degenerative impedance circuit coupled between the first differential transistor pair and ground. The first degenerative impedance includes switchable components to vary impedance of the first degenerative impedance circuit. The CTLE circuit also includes a second degenerative impedance circuit coupled between the second differential transistor pair and ground. The second degenerative impedance includes switchable components to vary impedance of the second degenerative impedance circuit, wherein the resistive part of the impedance of the first degenerative impedance circuit is equal to the impedance of the second degenerative impedance circuit.

A plurality of driver slice circuits arranged in parallel having a plurality of driver slice outputs, each driver slice circuit having a digital driver input and a driver slice output, each driver slice circuit configured to generate a signal level determined by the digital driver input, and a common output node connected to the plurality of driver slice outputs and a wire of a multi-wire bus, the multi-wire bus having a characteristic transmission impedance matched to an output impedance of the plurality of driver slice circuits arranged in parallel, each driver slice circuit of the plurality of driver slice circuits having an individual output impedance that is greater than the characteristic transmission impedance of the wire of the multi-wire bus.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Examples described herein relate to link training between network connected devices. In some examples, an amount to extend link training is determined. The amount to extend link training can be determined by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals indicating capability to extend link training time and amount to extend link training time; determining, at the first device, a link training time based on a default link training time and an amount to extend link training time; and performing link training based on the determined link training time. In some examples, the determined amount is highest common denominator of the received identified capability and transmitted indicated capability. In some examples, if the received communication indicates no ability to extend link training time, the link training time is a default link training time. In some examples, the signals indicating capability to extend link training time and amount to extend link training time comprise an IEEE 802.3 compatible Next Page.

Examples described herein relate to determining whether a device can re-train settings of one or more components of another device. Some examples include conducting link re-training by: receiving, by a receiver in a first device, signals over a lane from a transmitter in a second device, the signals comprising a first communication identifying capability to re-train a link; transmitting, from the first device, a second communication including one or more components of a second device with capability to be adjusted and a request to modify one or more parameters of the one or more components; and receiving, at the first device, a third communication identifying a status of re-training. In some examples, the one or more components comprise an equalizer and the one or more parameters comprises at least one tap setting. In some examples, the one or more parameters comprise a precursor, main cursor or post-cursor equalization setting.