What is provided is a transistor including a gate electrode, a gate insulating film, a semiconductor film, a source electrode, and a drain electrode, in which the gate insulating film is a laminated film in which a SiO.sub.x film and a SiC.sub.yN.sub.z film are alternately formed, the total number of films constituting the laminated film is 3 or more and 18 or less, and the thickness of each film constituting the laminated film is 25 nm or more and 150 nm or less.

The present application provides a method for manufacturing a metal gate, comprising: step 1: forming a polysilicon dummy gate on a semiconductor substrate; step 2: forming low dielectric constant sidewalls, comprising: step 21: forming a first protective layer; step 22: forming a second low dielectric constant layer; step 23: forming a third protective layer; and step 24: performing blank etching, and forming the low dielectric constant sidewalls by stacking the first protective layer, the second low dielectric constant layer, and the third protective layer on the side surfaces of the polysilicon dummy gate; step 3: forming a zeroth interlayer film; and step 4: performing gate replacement, comprising: step 41: removing the polysilicon dummy gate, and forming a gate trench; and step 42: forming a metal gate in the gate trench.

Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill.

There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.

A method of forming a silicon nitride film on a substrate having a recess pattern formed in a surface thereof, includes: forming the silicon nitride film in conformity to the surface of the substrate by supplying each of a raw material gas containing silicon and a nitriding gas for nitriding the raw material gas into a processing container in which the substrate is accommodated; shrinking the silicon nitride film such that a thickness thereof is reduced from a bottom side toward an upper side of the recess pattern by supplying a plasmarized shaping gas for shaping the silicon nitride film to the substrate in a state where the supply of the raw material gas containing silicon into the processing container is stopped; and burying the silicon nitride film in the recess pattern by alternately and repeatedly performing the forming the silicon nitride film and the shrinking the silicon nitride film.

Methods and systems for selective deposition of conductive a cap for FAV features are described. In an embodiment, a method may include receiving a substrate having an interlayer dielectrics (ILD) layer, the ILD layer having a recess, the recess having a conductive layer formed therein, the conductive layer comprising a first conductive material. Additionally, such a method may include forming a cap within a region defined by the recess and in contact with a surface of the conductive layer, the cap comprising a second conductive material. The method may also include forming a conformal etch stop layer in contact with a surface of the cap and in contact with a region of the ILD layer. Further, the method may include selectively etching the etch stop layer using a plasma etch process, wherein the plasma etch process removes the etch stop layer selective to the second conductive material comprising the cap.

A SiC film structure for obtaining a three-dimensional SiC film by forming the SiC film in an outer circumference of a substrate using a vapor deposition type film formation method and removing the substrate, the SiC film structure including: a main body having a three-dimensional shape formed of a SiC film and having an opening for removing the substrate; a lid configured to cover the opening; and a SiC coat layer configured to cover at least a contact portion between the main body and an outer edge portion of the lid and join the main body and the lid.

A semiconductor structure and a method for forming the same are provided. In one form, the method includes: providing a base, a gate structure being formed on the base, a source/drain doped layer being formed within the base on both sides of the gate structure, and an initial dielectric layer being formed on the base exposed from the gate structure, the initial dielectric layer covering a top of the gate structure, and a source/drain contact plug electrically connected to the source/drain doped layer being formed within the initial dielectric layer on the top of the source/drain doped layer; removing a portion of a thickness of the initial dielectric layer to form a dielectric layer exposing a portion of a side wall of the source/drain contact plug; forming an etch stop layer on at least the side wall of source/drain contact plug exposed from the dielectric layer; etching the dielectric layer on the top of the gate structure using etch stop layers on side walls of adjacent source/drain contact plugs as lateral stop positions, to form a gate contact exposing the top of the gate structure; forming, within the gate contact, a gate contact plug electrically connected to the gate structure. Implementations of the present disclosure facilitate enlargement of a process window for forming a contact over active gate.

A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a third source/drain feature, a first dummy fin disposed between the first source/drain feature and the second source/drain feature along a direction to isolate the first source/drain feature from the second source/drain feature, and a second dummy fin disposed between the second source/drain feature and the third source/drain feature along the direction to isolate the second source/drain feature from the third source/drain feature. The first dummy fin includes an outer dielectric layer, an inner dielectric layer over the outer dielectric layer, and a first capping layer disposed over the outer dielectric layer and the inner dielectric layer. The second dummy fin includes a base portion and a second capping layer disposed over the base portion.

A method for manufacturing a semiconductor device is provided. The method includes a step of performing a chemical mechanical polishing process on a first silicon oxide layer to form a planar surface layer; surface treatment is performed on the planar surface layer to form a treated planarization layer, and a second silicon oxide layer is formed on the treated planarization layer.