A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm.sup.2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.

Non-conductive substrates, especially the sidewalls of micro/nano holes thereof are chemically modified (i.e., chemically grafted) by reduced graphene oxide (rGO). The rGO possesses excellent electrical conductivity and therefore the modified substrates become conductive, so that it can be directly electroplated. These rGO-grafted holes can pass thermal shock reliability test after electroplating. The rGO grafting process possesses many advantages, such as a short process time, no complex agent (i.e., no chelator), no toxic agents (i.e., formaldehyde for electroless Cu deposition). It is employed in an aqueous solution instead of an organic solvent, and therefore is environmentally friendly and beneficial for industrial production.

A semiconductor structure includes an insulating substrate, an engineered layer, a semiconductor layer, a gate structure, a source region, and a drain region. The engineered layer is surrounding the insulating substrate. The semiconductor layer including a first region and a second region is formed over the engineered layer. The gate structure is formed over the semiconductor layer. The source region and the drain region are formed in the semiconductor layer and located on both sides of the first gate structure.

A process for growing nanowires or nanopyramids comprising: (I) providing a graphitic substrate and depositing AlGaN, InGaN, AlN or AlGa(In)N on said graphitic substrate at an elevated temperature to form a buffer layer or nanoscale nucleation islands of said compounds; (II) growing a plurality of semiconducting group III-V nanowires or nanopyramids, preferably III-nitride nanowires or nanopyramids, on the said buffer layer or nucleation islands on the graphitic substrate, preferably via MOVPE or MBE.

The present disclosure describes porous GaN layers and/or compliant substrates used to enable relaxation of previously strained top layers and the deposition of relaxed or partially relaxed on top. Relaxed In GaN layers are fabricated without generation of crystal defects, which can serve as base layers for high performance long wavelength light emitting devices (LEDs, lasers) solar cells, or strain engineered transistors. Similarly, relaxed AlGaN layers can serve as base layers for high performance short wavelength UV light emitting devices (LEDs, lasers) solar cells, or wide bandgap transistors.

A method of positioning nanomaterials includes patterning guiding dielectric features from a single layer of guiding dielectric material, and producing an electric field by at least one electrode disposed on a substrate that is attenuated through the guiding dielectric features to create an attractive dielectrophoretic force that guides at least one nanostructure abutting the guiding dielectric features to be positioned on a deposition surface of the substrate.

The semiconductor manufacturing device includes: a lower substrate support base configured to support a diamond substrate; an upper substrate support base configured to support a semiconductor substrate; a support base drive unit configured to move the lower substrate support base and the upper substrate support base to bring the diamond substrate and the semiconductor substrate into close contact with each other under a state in which a pressure is applied to the diamond substrate and the semiconductor substrate in a thickness direction; and a second mechanism configured to deform a surface of the upper substrate support base opposed to the lower substrate support base so that a surface of the semiconductor substrate opposed to the diamond substrate forms a parallel surface or a parallel plane with respect to a surface of the diamond substrate opposed to the semiconductor substrate.

A composition of matter comprising a film on a graphitic substrate, said film having been grown epitaxially on said substrate, wherein said film comprises at least one group III-V compound or at least one group II-VI compound.

A method of preparing a diamond crystal substrate for epitaxial deposition thereupon of a delta doping layer includes preparing an atomically smooth, undamaged diamond crystal substrate surface, which can be in the (100) plane, by polishing the surface and then etching the surface to remove subsurface damage caused by the polishing. The polishing can include a rough polish, for example in the (010) direction, followed by a fine polish, for example in the (011) direction, that removes the polishing tracks from the rough polishing. After etching the polished face can have a roughness Sa of less than 0.3 nm. An inductively coupled reactive ion etcher can apply the etching at a homogeneous etch rate using an appropriate gas mixture such as using argon and chlorine to remove between 0.1 and 10 microns of material from the polished surface.

Methods of fabricating compound semiconductor device structures having polycrystalline CVD diamond. The method includes: providing a substrate that has a layer of single crystal compound semiconductor material; forming a bonding layer on a surface of the substrate, the bonding layer having a thickness of less than 25 nm and a thickness variation of no more than 15 nm; and growing a layer of polycrystalline diamond on the bonding layer using a chemical vapor deposition technique. The effective thermal boundary resistance at the interface between the layer of single crystal compound semiconductor material and the layer of polycrystalline CVD diamond material is less than 25 m.sup.2K/GW. The layer of single crystal compound semiconductor material has one or both of the following characteristics: a charge mobility of at least 1200 cm.sup.2V.sup.1s.sup.1; and a sheet resistance of no more than 700 /square.