Methods and wafers for vertical gradient freeze 8 inch gallium arsenide (GaAs) substrates. In disclosed examples, vertical gradient freeze systems for forming gallium arsenide (GaAs) substrates having silicon as a dopant, the system includes a crucible to contain a GaAs liquid melt and seed material during a formation process; one or more heating coils arranged in a plurality of heating zones; and a pedestal to move relative to the crucible, the system operable to control heating of the plurality of heating zones and movement of the pedestal to form a single crystal GaAs substrate.

A method of performing heteroepitaxy comprises exposing a substrate to a carrier gas, a first precursor gas, a Group II/III element, and a second precursor gas, to form a heteroepitaxial growth of one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN on the substrate; wherein the substrate comprises one of GaAs, AlAs, InAs, GaP, InP, ZnSe, GaSe, CdSe, InSe, ZnTe, CdTe, GaTe, HgTe, GaSb, InSb, AlSb, CdS, GaN, and AlN; wherein the carrier gas is H.sub.2, wherein the first precursor is HCl, the Group II/III element comprises at least one of Zn, Cd, Hg, Al, Ga, and In; and wherein the second precursor is one of AsH.sub.3 (arsine), PH.sub.3 (phosphine), H.sub.2Se (hydrogen selenide), H.sub.2Te (hydrogen telluride), SbH.sub.3 (hydrogen antimonide), H.sub.2S (hydrogen sulfide), and NH.sub.3 (ammonia). The process may be an HVPE (hydride vapor phase epitaxy) process.

A microelectronic device includes a gated graphene component over a semiconductor material. The gated graphene component includes a graphitic layer having at least one layer of graphene. The graphitic layer has a channel region, a first connection and a second connection make electrical connections to the graphitic layer adjacent to the channel region. The graphitic layer is isolated from the semiconductor material. A backgate region having a first conductivity type is disposed in the semiconductor material under the channel region. A first contact field region and a second contact field region are disposed in the semiconductor material under the first connection and the second connection, respectively. At least one of the first contact field region and the second contact field region has a second, opposite, conductivity type. A method of forming the gated graphene component in the microelectronic device with a transistor is disclosed.

A layered structure for semiconductor application is described herein. The layered structure includes III-V semiconductor and uses pnictide nanocomposites to control lattice distortion in a series of layers. The distortion is tuned to bridge lattice mismatch between binary III-V semiconductors. In some embodiments, the layered structure further includes dislocation filters.

A vapor phase epitaxy method including: providing a III-V substrate of a first conductivity type, introducing the III-V substrate into a reaction chamber of a vapor phase epitaxy system at a loading temperature, heating the III-V substrate from the loading temperature to an epitaxy temperature while introducing an initial gas flow, depositing a III-V layer with a dopant concentration of a dopant of the first conductivity type on a surface of the III-V substrate from the vapor phase from an epitaxial gas flow, fed into the reaction chamber and comprising the carrier gas, the first precursor, and at least one second precursor for an element of main group III, wherein during the heating from the loading temperature to the epitaxy temperature, a third precursor for a dopant of the first conductivity type is added to the initial gas flow.

The present disclosure provides a semiconductor heterojunction. The semiconductor heterojunction includes a bottom semiconductor, a top semiconductor and an electrode substrate. An upper surface of the bottom semiconductor includes a first facet. A lower surface of the top semiconductor includes a second facet, and the lower surface of the top semiconductor is contacted with the upper surface of the bottom semiconductor. The electrode substrate is disposed below the bottom semiconductor.

A stacked high-blocking III-V power semiconductor diode, with a p+ or n+ substrate layer, a p− layer, an n− region with a layer thickness of 10 μm-150 μm, and an n+ or p+ layer, wherein all layers comprise a GaAs compound, a first metallic contact layer and a second metallic contact layer and a hard mask layer with at least one seed opening, wherein the hard mask layer is integrally bonded to the substrate layer or integrally bonded to the p− layer, the n− region extends within the seed opening and over an edge region, adjacent to the seed opening, of a top side of the hard mask layer and the n− region within the seed opening is integrally bonded to the p− layer or to the n+ substrate layer and in the edge region of the top side of the hard mask layer to the hard mask layer.

A method of producing graphene or other two-dimensional material such as graphene including heating the substrate held within a reaction chamber to a temperature that is within a decomposition range of a precursor, and that allows two-dimensional crystalline material formation from a species released from the decomposed precursor; establishing a steep temperature gradient (preferably >1000° C. per meter) that extends away from the substrate surface towards an inlet for the precursor; and introducing precursor through the relatively cool inlet and across the temperature gradient towards the substrate surface. The steep temperature gradient ensures that the precursor remains substantially cool until it is proximate the substrate surface thus minimizing decomposition or other reaction of the precursor before it is proximate the substrate surface. The separation between the precursor inlet and the substrate is less than 100 mm.

Provided is a nanowire array, in which a plurality of nanowires are densely packed and in contact with each other via side walls to form a three-dimensional, compact layer structure, wherein the plurality of nanowires are formed from InGaN-based material. Also provided is an optoelectronic device comprising the nanowire array which is epitaxially grown on a surface of a substrate (12). Further provided are methods for preparing the nanowire array and the optoelectronic device.

A semiconductor crystal substrate includes a crystal substrate that is formed of a material including GaSb or InAs, a first buffer layer that is formed on the crystal substrate and formed of a material including GaSb, the first buffer layer having n-type conductivity, and a second buffer layer that is formed on the first buffer layer and formed of a material including GaSb, the second buffer layer having p-type conductivity.