Patent classifications
H01L21/02505
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device comprises steps of: forming a semiconductor stack by growing an AlGaN layer or an InAlN layer, an AlN layer, and a GaN layer on a substrate in this order; forming a recess in the semiconductor stack by a dry etching from a surface of the semiconductor stack, the surface being opposite to the substrate; growing a GaN region in the recess; and forming an ohmic electrode on the GaN region; wherein in the forming of the recess, the dry etching is stopped in response to the recess reaching the AlN layer.
METHODS OF MANUFACTURING SEMICONDUCTOR STRUCTURE
The present application provides a method of manufacturing a semiconductor structure. The manufacturing method includes following steps: at step S1: forming a first epitaxial structure above a substrate, where the first epitaxial structure is doped with a doping element; at step S2: forming a sacrificial layer above the first epitaxial structure; at step S3: etching the sacrificial layer; at step S4: growing an insertion layer above the first epitaxial structure when the etching of the sacrificial layer is completed; and at step S5: growing a second epitaxial structure above the insertion layer; before proceeding to step S4, repeating step S2 and step S3, until a concentration of the doping element in the first epitaxial structure is lower than a predetermined threshold. In the present application, sacrificial layers are formed above the first epitaxial structure, and the sacrificial layers are repeatedly etched, so that the concentration of the doping element in the first epitaxial structure is lower than the predetermined threshold, thereby preventing the doping element in the first epitaxial structure from migrating upward into an upper epitaxial structure, ensuring a mobility of electrons in the upper epitaxial structure, so as to improve a performance of a device.
FABRICATION OF A SEMICONDUCTOR DEVICE INCLUDING A QUANTUM DOT STRUCTURE
The invention relates to a method for fabricating a semiconductor device. The method includes steps of providing a cavity structure, the cavity structure including a seed area including a seed material. The method further includes growing, within the cavity structure, a first embedding layer in a first growth direction from a seed surface of the seed material. The method includes further steps of removing the seed material, growing, in a second growth direction, from a seed surface of the first embedding layer, a quantum dot structure and growing, within the cavity structure, on a surface of the quantum dot structure, a second embedding layer in the second growth direction. The second growth direction is different from the first growth direction. The invention further relates to devices obtainable by such a method.
Method and system for group IIIA nitride growth
A system and method for growing a gallium nitride (GaN) structure that includes providing a template; and growing at least a first GaN layer on the template using a first sputtering process, wherein the first sputtering process includes: controlling a temperature of a sputtering target, and modulating between a gallium-rich condition and a gallium-lean condition, wherein the gallium-rich condition includes a gallium-to-nitrogen ratio having a first value that is greater than 1, and wherein the gallium-lean condition includes the gallium-to-nitrogen ratio having a second value that is less than the first value. Some embodiments include a load lock configured to load a substrate wafer into the system and remove the GaN structure from the system; and a plurality of deposition chambers, wherein the plurality of deposition chambers includes a GaN-deposition chamber configured to grow at least the first GaN layer on a template that includes the substrate wafer.
Process and manufacture of low-dimensional materials supporting both self-thermalization and self-localization
Various articles and devices can be manufactured to take advantage of a what is believed to be a novel thermodynamic cycle in which spontaneity is due to an intrinsic entropy equilibration. The novel thermodynamic cycle exploits the quantum phase transition between quantum thermalization and quantum localization. Preferred devices include a phonovoltaic cell, a rectifier and a conductor for use in an integrated circuit.
NITRIDE SEMICONDUCTOR COMPONENT AND PROCESS FOR ITS PRODUCTION
A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm.sup.2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.
Method for Forming Semiconductor Layers
A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.
SUBSTRATE FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME
The present invention provides a substrate for a semiconductor device and a semiconductor device using the same. The substrate for a semiconductor device comprises a ceramic supporting base plate formed by a polycrystalline aluminum nitride (AlN) sintered body; at least one silicon oxide layer formed on the base plate by a sol-gel method wherein the at least one silicon oxide layer has an average roughness less than the base plate to block polycrystalline orientation of the base plate and has a total thickness in a range of 10˜5000 nm, the silicon oxide layer is only formed from the sol-gel method and are not single crystalline; a first buffer layer comprising aluminum nitride (AlN) on the at least one silicon oxide layer with a thickness of 0.1˜10 μm; and a gallium nitride layer formed on the first buffer layer and having a single-crystal crystalline structure.
Semiconductor multilayer structure
A semiconductor device includes a substrate comprising a layer made of Ge and a semiconductor multilayer structure grown on the layer made of Ge. The semiconductor multilayer structure includes at least one first layer comprising a material selected from a group consisting of Al.sub.xGa.sub.1-xAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zP.sub.z, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-zN.sub.z, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zP.sub.c, Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cN.sub.zSb.sub.c, and Al.sub.xGa.sub.1-x-yIn.sub.yAs.sub.1-z-cP.sub.zSb.sub.c, wherein for any material a sum of the contents of all group-III elements equals 1 and a sum of the contents of all group-V elements equals 1. The semiconductor multilayer structure also includes at least one second layer comprising a material selected from a group consisting of GaInAsNSb, GaInAsN, AlGaInAsNSb, AlGaInAsN, GaAs, GaInAs, GaInAsSb, GaInNSb, GaInP, GaInPNSb, GaInPSb, GaInPN, AlInP, AlInPNSb, AlInPN, AlInPSb, AlGaInP, AlGaInPNSb, AlGaInPN, AlGaInPSb, GaInAsP, GaInAsPNSb, GaInAsPN, GaInAsPSb, GaAsP, GaAsPNSb, GaAsPN, GaAsPSb, AlGaInAs and AlGaAs.
Method for epitaxial growth and device
A semiconductor device includes first and second semiconductor fins extending from a substrate and a source/drain region epitaxially grown in recesses of the first and second semiconductor fins. A top surface of the source/drain region is higher than a surface level with top surfaces of the first and second semiconductor fins. The source/drain region includes a plurality of buffer layers. Respective layers of the plurality of buffer layers are embedded between respective layers of the source/drain region.