A method of forming an LED emitter includes: providing a III-nitride layer on a substrate (310), the III-nitride layer having a planar top surface; providing discrete lateral growth regions on the top surface; selectively epitaxially growing, on each discrete lateral growth region, a base region (1210) comprising an In(x)Ga(1-x)N material, each extending perpendicular to the top surface; providing surfaces of the In(x)Ga(1-x)N material on portions of the base regions (1210), the surfaces having a relaxed strain and being characterized by a base lattice constant within 0.1% of its bulk relaxed value; and epitaxially growing LED regions on the surfaces, the LED regions including light-emitting layers of In(y)Ga(1-y)N material that are pseudomorphic with the surfaces of the In(x)Ga(1-x)N material, and characterized by an active region (1240) lattice constant within 0.1% of the base lattice constant, wherein 0.05<x<0.2 and y>0.3.

A semiconductor substrate includes: a base substrate layer doped with a first type dopant; a first epitaxial layer on the base substrate layer that has a first thickness and is doped with the first type dopant to provide a first resistivity; a second epitaxial layer on the first epitaxial layer that has a second thickness and is doped with the first type dopant to provide a second resistivity (less than the third resistivity); and a third epitaxial layer on the second epitaxial layer that has a third thickness and is doped with the first type dopant to provide a third resistivity (less than the second resistivity). An oxide field trench transistor includes a trench with insulated polygate and polysource regions extending into the semiconductor substrate and passing through the first doped region, the second doped region, the third epitaxial layer and partially into the second epitaxial layer.

Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a semiconductor structure with a p-type superlattice region, an i-type superlattice region, and an n-type superlattice region is disclosed. The semiconductor structure can have a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. In some cases, there are no abrupt changes in polarisation at interfaces between each region. At least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region can comprise a plurality of unit cells exhibiting a monotonic change in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer orderly. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1−x)In.sub.xN, where 0≤x≤1. The x value consists of four sections of variation along the thickness direction, in which a first fixed region has a maximum value, a first gradient region gradually changes from the maximum value to a minimum value, a second fixed region has the minimum value, and a second gradient region gradually changes from the minimum value to the maximum value. An absolute value of a gradient slope of the first and second gradient regions is 0.1%/nm to 50%/nm. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

A heterostructure, includes: a substrate; and a buffer layer that includes a plurality of layers having a composition Al.sub.xIn.sub.yGa.sub.1-x-yN, where x≤1 and 0≤y≤1; wherein the buffer layer has a first region that includes at least two layers, a second region that includes at least two layers, and a third region that includes at least two layers. The aluminum content varies continuously throughout a thickness of at least one of the layers.

An epitaxial structure includes a substrate, a nucleation layer on the substrate, a buffer layer on the nucleation layer, and a nitride layer on the buffer layer. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al.sub.(1−x)In.sub.xN, where 0≤x≤1. A maximum value of the x value in the regions decreases along the thickness direction, and the x value in the chemical composition of each two regions consists of a fixed region and a gradient region, wherein a gradient slope of the gradient regions is −0.1%/nm to −50%/nm, and a stepwise slope of the fixed regions is −0.1%/loop to −50%/loop. A thickness of the nucleation layer is less than that of the buffer layer. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.

Methods and structures includes providing a substrate, forming a prelayer over a substrate, forming a barrier layer over the prelayer, and forming a channel layer over the barrier layer. Forming the prelayer may include growing the prelayer at a graded temperature. Forming the barrier layer is such that the barrier layer may include GaAs or InGaAs. Forming the channel layer is such that the channel layer may include InAs or an Sb-based heterostructure. Thereby structures are formed.

A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.