Apparatuses and methods are provided for manufacturing diamond electronic devices. The method includes at least one of the following acts: positioning a substrate in a plasma enhanced chemical vapor deposition (PECVD) reactor; controlling temperature of the substrate by manipulating microwave power, chamber pressure, and gas flow rates of the PECVD reactor; and growing phosphorus doped diamond layer on the substrate using a pulsed deposition comprising a growth cycle and a cooling cycle.

A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.

Methods for growing microstructured and nanostructured graphene by growing the microstructured and nanostructured graphene from the bottom-up directly in the desired pattern are provided. The graphene structures can be grown via chemical vapor deposition (CVD) on substrates that are partially covered by a patterned graphene growth barrier which guides the growth of the graphene.

A semiconductor device includes a graphene film disposed on a substrate and formed of atomic layers of graphene that are stacked, a source electrode and a drain electrode disposed on the graphene film, and a gate electrode disposed on the graphene film between the source electrode and the drain electrode with a gate insulator film interposed between the gate electrode and the graphene film, wherein a first number of the atomic layers of the graphene film in a source region where the source electrode is located and a drain region where the drain electrode is located is greater than a second number of the atomic layers of the graphene film in a channel region where the gate electrode is located.

A graphene optical sensor includes a graphene layer having a surface, a first electrode and a second electrode, formed on the surface of the graphene layer, and arranged in a first direction parallel to the surface of the graphene layer, and a plurality of plasmonic antennas provided on the surface of the graphene layer between the first and second electrodes. Each plasmonic antenna of the plurality of plasmonic antennas, in a plan view, includes a first rod portion extending in a second direction inclined from the first direction, and a second rod portion extending in a third direction inclined from the first direction in a direction opposite the second direction with reference to the first direction, and intersecting the first rod portion. The plurality of the plasmonic antennas is arranged periodically in the second direction and in the third direction.

A stacked body includes: a substrate made of silicon carbide and having a first main surface forming an angle of 20° or less with a carbon plane; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of silicon carbide forming the substrate. In an exposed surface of the graphene film as seen in plan view, 10 or less regions are present per 1 mm.sup.2, the exposed surface being a main surface opposite to the substrate, and the regions each including 10 or more graphene layers and having a circumcircle with a diameter of 5 μm or more and 100 μm or less. Accordingly, the stacked body is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO.sub.2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO.sub.2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO.sub.2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO.sub.2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (V.sub.g) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

Described herein are solid-state devices based on graphene in a Field Effect Transistor (FET) structure that emits high frequency Electromagnetic (EM) radiation using one or more DC electric fields and periodic magnetic arrays or periodic nanostructures. A number of devices are described that are capable of generating and emitting electromagnetic radiation.

Some embodiments include an integrated assembly having a conductive structure, an annular structure extending through the conductive structure, and an active-material-structure lining an interior periphery of the annular structure. The annular structure includes dielectric material. The active-material-structure includes two-dimensional-material. Some embodiments include methods of forming integrated assemblies.

Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp.sup.2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.