A film deposition method may include preparing a non-planar substrate including a first surface, a second surface, and an inclined surface between the first surface and the second surface; depositing a film having a thickness deviation on the first surface, the second surface, and the inclined surface; and etching the film deposited on the first surface, the second surface, and the inclined surface. A height of the second surface may be different than a height of the first surface.

A method of forming regrown fiducials includes providing a III-V compound substrate having a device region and an alignment mark region. The III-V compound substrate is characterized by a processing surface. The method also includes forming a hardmask layer having a first set of openings in the device region exposing a first surface portion of the processing surface of the III-V compound substrate and a second set of openings in the alignment mark region exposing a second surface portion of the processing surface and etching the first surface portion and the second surface portion of the III-V compound substrate using the hardmask layer as a mask to form a plurality of trenches. The method also includes epitaxially regrowing a semiconductor layer in the trenches to form the regrown fiducials extending to a predetermined height over the processing surface in the alignment mark region.

A semiconductor device includes a channel layer configured to include a first nitride semiconductor containing gallium (Ga) and a first crystal dislocation density, and a barrier layer provided over a first surface side of the channel layer, and configured to include a second nitride semiconductor containing aluminum (Al) and a second crystal dislocation density, wherein the second crystal dislocation density is larger than the first crystal dislocation density.

Wafers including a diamond layer and a semiconductor layer having III-Nitride compounds and methods for fabricating the wafers are provided. A nucleation layer, at least one semiconductor layer having III-Nitride compound and a protection layer are formed on a silicon substrate. Then, a silicon carrier wafer is glass bonded to the protection layer. Subsequently the silicon substrate, nucleation layer and a portion of the semiconductor layer are removed. Then, an intermediate layer, a seed layer and a first diamond layer are sequentially deposited on the III-Nitride layer. Next, the silicon carrier wafer and the protection layer are removed. Then, a silicon substrate wafer that includes a protection layer, silicon substrate and a diamond layer is prepared and glass bonded to the first diamond layer.

A Group III-Nitride quantum well laser including a distributed Bragg reflector (DBR). In some embodiments, the DBR includes Scandium. In some embodiments, the DBR includes Al.sub.1-xSc.sub.xN, which may have 0<x≤0.45.

A substrate for an electronic device, including a nitride semiconductor film formed on a joined substrate including a silicon single crystal, where the joined substrate has a plurality of silicon single crystal substrates that are joined and has a thickness of more than 2000 μm, and the plurality of silicon single crystal substrates are produced by a CZ method and have a resistivity of 0.1 Ωcm or lower. This provides: a substrate for an electronic device having a nitride semiconductor film formed on a silicon substrate, where the substrate for an electronic device can suppress a warp and can also be used for a product with a high breakdown voltage; and a method for producing the same.

Embodiments of the present disclosure include techniques related to techniques for processing materials for manufacture of group-III metal nitride and gallium based substrates. More specifically, embodiments of the disclosure include techniques for growing large area substrates using a combination of processing techniques. Merely by way of example, the disclosure can be applied to growing crystals of GaN, AlN, InN, InGaN, AlGaN, and AlInGaN, and others for manufacture of bulk or patterned substrates. Such bulk or patterned substrates can be used for a variety of applications including optoelectronic and electronic devices, lasers, light emitting diodes, solar cells, photo electrochemical water splitting and hydrogen generation, photodetectors, integrated circuits, and transistors, and others.

A method for manufacturing a group III nitride substrate is described. The method involves forming group III nitride films having a group III element face on a surface thereof, on both surfaces of a substrate, so as to produce a group III nitride film carrier. The group III nitride film carrier is subjected to ion implantation and adhered to a base substrate containing polycrystals containing a group III nitride as a major component. The group III nitride film carrier is spaced from the base substrate to transfer the ion-implanted region to the base substrate, so as to form a group III nitride film having an N face on a surface thereof on the base substrate. A group III nitride film is formed on the group III nitride by a THVPE method, so as to produce a thick film of a group III nitride film.

There is provided a Group-III element nitride semiconductor substrate including a first surface and a second surface, in which even when devices to be produced on the first surface are increased in size, variations in device characteristics between the devices in the same substrate are suppressed. A Group-III element nitride semiconductor substrate includes a first surface and a second surface. The Group-III element nitride semiconductor substrate satisfies at least one of the following items (1) to (3): (1) The main surface has a maximum height Wz of a surface waviness profile of 150 nm or less; (2) The main surface has a root mean square height Wq of the surface waviness profile of 25 nm or less; (3) The main surface has an average length WSm of surface waviness profile elements of 0.5 mm or more.

Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.