Provided is a method of manufacturing a nanowire semiconductor device, the method including: forming a seed layer on a substrate; forming, on the seed layer, a multilayer in which a first conductive layer, a semiconductor layer, a second conductive layer are sequentially stacked; forming a vertical nanowire above the substrate by patterning the multilayer; crystallizing the vertical nanowire by heat treatment; forming an insulating layer covering the vertical nanowire; forming a gate surrounding a channel area by the semiconductor silicon layer of the vertical nanowire; and forming a metal pad electrically connected to the gate, the first conductive layer, and the second conductive layer.

A process for epitaxying GaSe on a [111]-oriented silicon substrate, includes a step of selecting a [111]-oriented silicon substrate resulting from cutting a silicon bar in a miscut direction which is one of the three [11-2] crystallographic directions, the miscut angle (α) being smaller than or equal to 0.1°, the obtained surface of the substrate forming a vicinal surface exhibiting a plurality of terraces and at least one step between two terraces; a passivation step consisting of depositing an atomic bilayer of gallium and of selenium on the vicinal surface of the silicon substrate so as to form a passivated vicinal surface made of silicon-gallium-selenium (Si—Ga—Se), said passivated vicinal surface exhibiting a plurality of passivated terraces and at least one passivated step between two passivated terraces; a step of forming a layer of two-dimensional GaSe by epitaxy on the passivated surface, said formation step comprising a step of nucleation from each passivated step and a step of lateral growth on the passivated terraces from the nuclei obtained in the nucleation step. A structure obtained by means of the epitaxying process is also provided.

Disclosed herein is a method for 2D epitaxial growth comprising: forming a single crystalline h-BN template; forming a plurality of nuclei by depositing a heterogeneous precursor on the h-BN template; and forming a heterogeneous structure layer by growing the plurality of deposited nuclei with a van der Waals epitaxial growth, wherein the heterogeneous structure layer is a single crystal.

Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.

Provided is a crystalline oxide film including: a plane tilted from a c-plane as a principal plane; gallium; and a metal in Group 9 of the periodic table, the metal in Group 9 of the periodic table among all metallic elements in the film having an atomic ratio of equal to or less than 23%.

High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

A semiconductor substrate is provided in the present disclosure. The semiconductor substrate includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer has a first lattice constant (L1) and the second semiconductor layer has a second lattice constant (L2). A ratio of a difference (L2-L1) between the second lattice constant (L2) and the first lattice constant (L1) to the first lattice constant (L1) is greater than 0.036.

Provided is a group III nitride laminate for improving device characteristics, including: an underlying substrate; a first layer that is formed on the underlying substrate and is made of aluminum nitride; and a second layer that is formed on the first layer and is made of gallium nitride, wherein the first layer has a thickness of more than 100 nm and 1 μm or less, a full width at half maximum of (0002) diffraction determined through X-ray rocking curve analysis is 250 seconds or less, and a full width at half maximum of (10-12) diffraction determined through X-ray rocking curve analysis is 500 seconds or less.

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

A semiconductor substrate in includes a buffer layer and a first crystalline layer. A bandgap of the first crystalline layer is smaller than a bandgap of a second layer. When a semiconductor wafer is formed as a transistor wafer, a channel of a transistor is formed at or near an interface between the first crystalline layer and the second layer. With a first electrode and a second electrode provided and a third electrode provided, when space charge redistribution, for emitting electrons and holes from a bandgap of a crystal positioned in the spatial region, is achieved by applying negative voltage to the third electrode or by applying positive voltage to the second electrode with the first electrode serving as a reference, an electron emission speed in the space charge redistribution is higher than a hole emission speed.