Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, an IC die may include a semiconductor substrate, a group III-Nitride or II-VI wurtzite layer disposed over the semiconductor substrate, and a plurality of buffer structures at least partially embedded in the group III-Nitride or II-VI wurtzite layer. In some embodiments, each of the plurality of buffer structures may include a central member disposed over the semiconductor substrate, a lower lateral member disposed over the semiconductor substrate and extending laterally away from the central member, and an upper lateral member disposed over the central member and extending laterally from the central member in an opposite direction from the lower lateral member. The plurality of buffer structures may be positioned in a staggered arrangement to terminate defects of the group III-Nitride or II-VI wurtzite layer. Other embodiments may be described and/or claimed.

Embodiments described herein include a method for forming a vertical hetero-stack and a device including a vertical hetero-stack. An example method is used to form a vertical hetero-stack of a first nanostructure and a second nanostructure arranged on an upper surface of the first nanostructure. The first nanostructure is formed by a first transition metal dichalcogenide, TMDC, material and the second nanostructure is formed by a second TMDC material. The example method includes providing the first nanostructure on a substrate. The method also includes forming a reactive layer of molecules on the first nanostructure along a periphery of the upper surface. The method further includes forming the second nanostructure by a vapor deposition process. The second TMDC material nucleates on the reactive layer of molecules along the periphery and grows laterally therefrom to form the second nanostructure on the upper surface.

A C-plane GaN substrate only mildly restricts the shape and dimension of a nitride semiconductor device formed on the substrate. The variation of an off-angle on the main surface of the substrate is suppressed. In the C-plane GaN substrate: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on the main surface; the number density of the facet growth area accompanied by a core among the plurality of facet growth areas is less than 5 cm.sup.−2 on the main surface; and, when any circular area of 4 cm diameter is selected from an area which is on the main surface and is distant by 5 mm or more from the outer peripheral edge of the substrate, the variation widths of an a-axis direction component and an m-axis direction component of an off-angle within the circular area is each 0.25 degrees or less.

A buffer layer is employed to fabricate diamond membranes and allow reuse of diamond substrates. In this approach, diamond membranes are fabricated on the buffer layer, which in turn is disposed on a diamond substrate that is lattice-matched to the diamond membrane. The weak bonding between the buffer layer and the diamond substrate allows ready release of the fabricated diamond membrane. The released diamond membrane is transferred to another substrate to fabricate diamond devices, while the diamond substrate is reused for another fabrication.

The present invention provides a method for producing a Group III nitride crystal, capable of producing a Group III nitride crystal in a large size with few defects and high quality. The method is a method for producing a Group III nitride crystal (13), including: a seed crystal selection step of selecting plural parts of a Group III nitride crystal layer (11) as seed crystals for generation and growth of Group III nitride crystals (13); a contact step of causing the surfaces of the seed crystals to be in contact with an alkali metal melt; a crystal growth step of causing a Group III element and nitrogen to react with each other under a nitrogen-containing atmosphere in the alkali metal melt to generate and grow the Group III nitride crystals (13), wherein the seed crystals are hexagonal crystals, in the seed crystal selection step, the seed crystals are arranged so that m-planes of the respective crystals grown from the seed crystals that are adjacent to each other do not substantially coincide with each other, and in the crystal growth step, the plural Group III nitride crystals (13) grown from the plural seed crystals by the growth of the Group III nitride crystals (13) are bound.

The present disclosure provides a fabrication of M-plane gallium nitride which is able to grow M-plane gallium nitride without the need of expensive substrates, such as LiAlO.sub.2, LiGaO.sub.2 or SiC. The fabrication of M-plane gallium nitride includes preparing a zinc oxide hexagonal prism having a growth face, and growing a gallium nitride layer on the growth face of the zinc oxide hexagonal prism. The growth face is an M-plane perpendicular to a direction of gravity.

The semiconductor device includes a first insulator over a substrate, a first oxide semiconductor over the first insulator, a second oxide semiconductor over the first oxide semiconductor, a first conductor and a second conductor in contact with the second oxide semiconductor, a third oxide semiconductor on the second oxide semiconductor and the first and second conductors, a second insulator over the third oxide semiconductor, and a third conductor over the second insulator. At least one of the first oxide semiconductor, the second oxide semiconductor, and the third oxide semiconductor has a crystallinity peak that corresponds to a (hkl) plane (h=0, k=0, l is a natural number) observed by X-ray diffraction using a Cu K-alpha radiation as a radiation source. The peak appears at a diffraction angle 2 theta greater than or equal to 31.3 degrees and less than 33.5 degrees.

Provides is a C-plane GaN substrate which, although formed from a GaN crystal grown so that surface pits are generated, is free from any inversion domain, and moreover, has a low spiral dislocation density in a gallium polar surface. Provides is a C-plane GaN substrate wherein: the substrate comprises a plurality of facet growth areas each having a closed ring outline-shape on a gallium polar surface; the spiral dislocation density is less than 1×10.sup.6 cm.sup.−2 anywhere on the gallium polar surface; and the substrate is free from any inversion domain. The C-plane GaN substrate may comprise a high dislocation density part having a dislocation density of more than 1×10.sup.7 cm.sup.−2 and a low dislocation density part having a dislocation density of less than 1×10.sup.6 cm.sup.−2 on the gallium polar surface.

A method for forming III-N structures of desired nanoscale dimensions is disclosed. The method is based on, first, providing a material to serve as a shell inside which a cavity can be formed, followed by using epitaxial growth to fill the cavity with III-N semiconductor(s). Filling a cavity of specified shape and dimensions with a III-N semiconductor results in formation of a III-N structure which has shape and dimensions defined by those of the cavity in the shell, advantageously enabling formation of III-N structures on a nanometer scale without having to rely on etching of III-N materials. Ensuring that at least a part of the III-N material in the cavity is formed by lateral epitaxial overgrowth allows obtaining high quality III-N semiconductor in that part without having to grow a thick layer. Disclosed III-N nanostructures can serve as foundation for fabricating III-N device components, e.g. III-N transistors, having non-planar architecture.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.