Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

A crystalline channel layer of a semiconductor material is formed in a backend process over a crystalline dielectric seed layer. A crystalline magnesium oxide MgO is formed over an amorphous inter-layer dielectric layer. The crystalline MgO provides physical link to the formation of a crystalline semiconductor layer thereover.

A method for manufacturing a Hall sensor, an insulation layer being initially applied to a wafer including an ASIC or integrated into the wafer, a Hall layer, for example, made of InSb or another III-V semiconductor material, being situated thereon, and this Hall layer being at least sectionally recrystallized with the aid of a laser. The insulation layer may be porous or may include a cavity or reflective layer for thermal protection of the ASIC.

A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.

A laser crystallization method includes exciting gas medium in an airtight container to generate laser beams; amplifying the laser beams by reflecting the laser beams between a high reflection mirror and a low reflection mirror respectively disposed facing opposite end portions of the airtight container, wherein a first transparent window and a second transparent window are fixed to respective end portions of the airtight container, and outputting the amplified laser beams; and disposing a cleaning mirror in a path of the laser beams that have propagated through the second transparent window.

A thermal processing apparatus and method in which a first laser source, for example, a CO.sub.2 emitting at 10.6 μm is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO.sub.2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.

A method of forming a crystalline silicon film includes forming a first amorphous silicon film on a substrate, forming a crystal nucleation film in which crystal nuclei of silicon are formed by performing a first annealing on the substrate having the first amorphous silicon film formed thereon, performing etching with an etching gas, forming a second amorphous silicon film on the crystal nuclei remaining after the etching, and forming a crystalline silicon film by performing a second annealing on the substrate after the forming of the second amorphous silicon film to grow the crystal nuclei.

Systems and methods for etching complex patterns on an interior surface of a hollow object are disclosed. A method generally includes positioning a laser system within the hollow object with a focal point of the laser focused on the interior surface, and operating the laser system to form the complex pattern on the interior surface. Motion of the laser system and the hollow object is controlled by a motion control system configured to provide rotation and/or translation about a longitudinal axis of one or both of the hollow object and the laser system based on the complex pattern, and change a positional relationship between a reflector and a focusing lens of the laser system to accommodate a change in distance between the reflector and the interior surface of the hollow object.

Provided are a method of manufacturing a thin film transistor, a dehydrogenating apparatus for performing the method, and an organic light emitting display device including a thin film transistor manufactured by the same. A method of manufacturing a thin film transistor includes reducing a content of oxygen in a chamber for performing a dehydrogenation process of an amorphous silicon layer from a first value to a second value, inserting a substrate on which the amorphous silicon layer is formed into the chamber, heating the inside of the chamber to perform the dehydrogenation process on the amorphous silicon layer, and forming a polysilicon layer by crystallizing the amorphous silicon layer using a laser.

Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting layer; make first crystalline semiconductor portions on the second source and drain regions; make the second regions amorphous and dope them; recrystallise the second regions and activate the dopants present in the second regions; remove the first portions; make a second spacer thicker than the first spacer; make second doped crystalline semiconductor portions on the second regions, said second portions and the second regions of the first layer together form the source and drain of the transistor.