A method includes providing a substrate having a first region and a second region, forming a fin protruding from the first region, where the fin includes a first SiGe layer and a stack alternating Si layers and second SiGe layers disposed over the first SiGe layer and the first SiGe layer has a first concentration of Ge and each of the second SiGe layers has a second concentration of Ge that is greater than the first concentration, recessing the fin to form an S/D recess, recessing the first SiGe layer and the second SiGe layers exposed in the S/D recess, where the second SiGe layers are recessed more than the first SiGe layer, forming an S/D feature in the S/D recess, removing the recessed first SiGe layer and the second SiGe layers to form openings, and forming a metal gate structure over the fin and in the openings.

A production method for a semi-conductor-on-insulator type multilayer stack includes ion implantation in a buried portion of a superficial layer of a support substrate, so as to form a layer enriched with at least one gas, intended to form a porous semi-conductive material layer, the thermal oxidation of a superficial portion of the superficial layer to form an oxide layer extending from the surface of the support substrate, the oxidation and the implantation of ions being arranged such that the oxide layer and the enriched layer are juxtaposed, and the assembly of the support substrate and of a donor substrate.

A microelectronic device may have side surfaces each including a first portion and a second portion. The first portion may have a highly irregular surface topography extending from an adjacent surface of the microelectronic device. The second portion may have a less uneven surface extending from the first portion to an opposing surface of the microelectronic device. Methods of forming the microelectronic device may include creating dislocations in the wafer in a street between the one or more microelectronic devices by implanting ions and cleaving the wafer responsive to failure of stress concentrations near the dislocations through application of heat, tensile forces or a combination thereof. Related packages and methods are also disclosed.

According to an embodiment, provided is a semiconductor device including: a first electrode; a second electrode; and a silicon carbide layer disposed between the first electrode and the second electrode, the silicon carbide layer including: a first silicon carbide region of an n-type; and a second silicon carbide region disposed between the first silicon carbide region and the first electrode, the second silicon carbide being in contact with the first electrode, and the second silicon carbide containing one oxygen atom bonding with four silicon atoms.

A semiconductor device is provided. The semiconductor device includes a substrate, device isolation films defining an active region in the substrate, the active region defined in the substrate by the device isolation films, a gate pattern formed in the active region, and source/drain regions on both sides of the gate pattern, in the active region, the source/drain regions include first parts, which are doped with carbon monoxide (CO) ions and are recrystallized.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.

A method of manufacturing a semiconductor device in a semiconductor body having a first surface and a second surface is proposed. The method includes implanting protons through the second surface into the semiconductor body. The method further includes implanting ions through the second surface into the semiconductor body. The ions are ions of a non-doping element having an atomic number of at least 9. Thereafter, the method further includes processing the semiconductor body by thermal annealing.

A silicon carbide semiconductor device includes a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a first semiconductor region, and a gate electrode. Protons are implanted in a first region spanning a predetermined distance from a surface of the semiconductor substrate facing toward the first semiconductor layer, in a second region spanning a predetermined distance from a surface of the first semiconductor layer on the second side of the first semiconductor layer facing toward the semiconductor substrate, in a third region spanning a predetermined distance from a surface of the first semiconductor layer on the first side of the first semiconductor layer facing toward the second semiconductor layer, and in a fourth region spanning a predetermined distance from a surface of the second semiconductor layer on the second side of the second semiconductor layer facing toward the first semiconductor layer.

A structure includes a semiconductor substrate, and a polycrystalline resistor region over the semiconductor substrate. The polycrystalline resistor region includes a semiconductor material in a polycrystalline morphology. A dopant-including polycrystalline region is between the polycrystalline resistor region and the semiconductor substrate.

Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.