In a substrate processing method according to the embodiment, a first material is implanted into a surface of a target film to modify the surface of the target film. The surface of the target film is dissolved to remove the surface of the target film by bringing a catalytic material close to the surface of the target film or by contacting the catalytic material to the surface of the target film while supplying a process solution on the surface of the target film which has been modified.

A method of preparing an iron-implanted semiconductor wafer for use in surface photovoltage iron mapping and other evaluation techniques. A semiconductor wafer is implanted with iron through the at least two different regions of the front surface of the semiconductor at different iron implantation densities, and the iron-implanted semiconductor wafer is annealed at a temperature and duration sufficient to diffuse implanted iron into the bulk region of the semiconductor wafer.

In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

A semiconductor device includes an active device region and a plurality of guard rings arranged in a first concentric pattern surrounding the active device region. The semiconductor device also includes a plurality of junctions arranged in a second concentric pattern surrounding the active device region. At least one of the plurality of junctions is arranged between two adjacent guard rings of the plurality of guard rings, and the plurality of junctions have a different resistivity than the plurality of guard rings. The semiconductor device further includes a plurality of coupling paths. At least one of the plurality of coupling paths is arranged to connect two adjacent guard rings of the plurality of guard rings.

An ion implantation method includes changing an ion acceleration energy and/or an ion beam current density of an ion beam while effecting a relative movement between a semiconductor substrate and the ion beam impinging on a surface of the semiconductor substrate.

A method of fabricating a high electron mobility transistor is disclosed. The method comprises using an ion implantation process to amorphize a portion of the barrier layer to a specific depth. The etch rate of this amorphized portion is much faster than that of the rest of the barrier layer. In this way, the depth of the recessed regions into which the source and drain contacts are disposed is more tightly controlled. Further, the etching process may be a wet or dry etch process. The roughness of the recessed region may also be improved using this approach.

A semiconductor device having a back-side field plate includes a buffer layer that includes a first compound semiconductor material, where the buffer layer is epitaxial to a crystalline substrate. The semiconductor device also includes field plate layer that is disposed on a surface of the buffer layer. The semiconductor device further includes a first channel layer disposed over the field plate layer, where the first channel layer includes the first compound semiconductor material. The semiconductor device further includes a region comprising a two-dimensional electron gas, where the two-dimensional electron gas is formed at an interface between the first channel layer and a second channel layer. The semiconductor device additionally includes a back-side field plate that is formed by a region of the field plate layer and is electrically isolated from other regions of the field plate layer.

An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

A HEMT transistor has a semiconductor layer structure that comprises a Group III nitride-based channel layer and a higher bandgap Group III nitride-based barrier layer on the channel layer. A gate finger and first and second source/drain contacts are provided on the semiconductor layer structure. A first source/drain region is provided in the semiconductor layer structure that includes a first implanted region that is underneath the first source/drain contact and a first auxiliary implanted region. A depth of the first implanted region is at least twice a depth of the first auxiliary implanted a region. The first source/drain region extends inwardly a first distance from a lower edge of an inner sidewall of the first source/drain contact, and extends outwardly a second smaller distance from a lower edge of an outer sidewall of the first source/drain contact.

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a barrier layer on the buffer layer; forming a hard mask on the barrier layer; performing an implantation process through the hard mask to form a doped region in the barrier layer and the buffer layer; removing the hard mask and the barrier layer to form a first trench; forming a gate dielectric layer on the hard mask and into the first trench; forming a gate electrode on the gate dielectric layer; and forming a source electrode and a drain electrode adjacent to two sides of the gate electrode.