The present invention relates to technology for fabricating a gallium nitride substrate using an ion implantation process to which a self-separation technique is applied. According to the present invention, a method of fabricating a gallium nitride substrate may include a step of forming a first gallium nitride layer on a substrate, a step of implanting hydrogen ions into the first gallium nitride layer to form a separation layer, a step of grinding the edges of the substrate, the first gallium nitride layer, and the separation layer, a step of forming a second gallium nitride layer on the first gallium nitride layer having a ground edge, and a step of self-separating the second gallium nitride layer from the first gallium nitride layer having a ground edge.

A display device includes an ion implantation region, a first semiconductor layer, an active layer under the first semiconductor layer, and a second semiconductor layer under the active layer. The ion implantation region includes a plurality of ions and partitions the active layer into a plurality of light-emitting regions, and an average ion concentration ratio of each of the light-emitting regions is 2 to 15.

A GaN layer of micro-LEDs is exposed to ion implantation to amorphize one or more regions of the GaN layer. As a result, the GaN layer through which light rays propagate have non-uniform refractive indexes that modify propagation paths of some light rays. Ions are implanted in a region overlapping an active region that emits light to function as a converging GRIN (gradient-index) lens. The ion implanted regions collimate light rays that propagate along predetermined directions. As such, the light extraction from and the focus of the micro-LEDs is increased.

A method for manufacturing a vertical FET device includes providing a semiconductor substrate structure including a semiconductor substrate and a first semiconductor layer coupled to the semiconductor substrate. The first semiconductor layer is characterized by a first conductivity type. The method also includes forming a plurality of semiconductor fins coupled to the first semiconductor layer. Each of the plurality of semiconductor fins is separated by one of a plurality of recess regions. The method further includes epitaxially regrowing a semiconductor gate layer including a surface region in the plurality of recess regions. The method also includes forming an isolation region within the surface region of the semiconductor gate layer. The isolation region surrounds each of the plurality of semiconductor fins. The method includes forming a source contact structure coupled to each of the plurality of semiconductor fins and forming a gate contact structure coupled to the semiconductor gate layer.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

A method of manufacturing an electronic device, including the successive steps of: a) performing an ion implantation of indium or of aluminum into an upper portion of a first single-crystal gallium nitride layer, to make the upper portion of the first layer amorphous and to preserve the crystal structure of a lower portion of the first layer; and b) performing a solid phase recrystallization anneal of the upper portion of the first layer, resulting in transforming the upper portion of the first layer into a crystalline indium gallium nitride or aluminum gallium nitride layer.

A method includes providing a single crystal substrate having a buffer layer on a surface of the substrate. The buffer layer provides a transition between the crystallographic lattice structure of the substrate and the crystallographic lattice structure of the semiconductor layer and has its resistivity increased by ion implanting a dopant into the buffer layer; and forming semiconductor layer on the ion implanted buffer layer. The semiconductor layer may be a wide bandgap semiconductor layer having a high electron mobility transistors formed therein.

A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A nitride semiconductor substrate is manufactured by a method which includes growing nitride semiconductor crystal along a c-axis direction on a +C-plane of a seed crystal substrate formed of nitride semiconductor crystal to form an n.sup.−-type first nitride semiconductor layer; growing the nitride semiconductor crystal along the c-axis direction on the +C-plane of the first nitride semiconductor layer to form a second nitride semiconductor layer; and removing the seed crystal substrate and exposing a −C-plane of the first nitride semiconductor layer to obtain as a semiconductor substrate a laminate of the first nitride semiconductor layer and the second nitride semiconductor layer, with the −C plane as a main surface.

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.