H01L21/26566

METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGE SENSING DEVICE
20200127044 · 2020-04-23 · ·

An object is to provide a method of producing a semiconductor epitaxial wafer having higher gettering capability and a reduced haze level of the surface of a semiconductor epitaxial layer.

The method of producing a semiconductor epitaxial wafer, according to the present invention includes: a first step of irradiating a semiconductor wafer 10 with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion 10A of the semiconductor wafer; a second step of performing heat treatment for crystallinity recovery on the semiconductor wafer 10 after the first step such that the haze level of the semiconductor wafer surface portion 10A is 0.20 ppm or less; and a third step of forming an epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer after the second step.

SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING SEMICONDUCTOR EPITAXIAL WAFER, AND METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE
20200126796 · 2020-04-23 · ·

Provided is a semiconductor epitaxial wafer in which the concentration of hydrogen in a modifying layer can be maintained at a high level and the crystallinity of an epitaxial layer is excellent. A semiconductor epitaxial wafer has a semiconductor wafer, a modifying layer formed in a surface portion of the semiconductor wafer, which modifying layer has hydrogen contained as a solid solution in the semiconductor wafer, and an epitaxial layer formed on the modifying layer. The concentration profile of hydrogen in the modifying layer in the thickness direction from a surface of the epitaxial layer is a double peak concentration profile including a first peak shallower in the depth direction and a second peak deeper in the depth direction.

Method of producing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method of producing solid-state image sensor
10629648 · 2020-04-21 · ·

A production method for a semiconductor epitaxial wafer includes: irradiating a surface of a semiconductor wafer with cluster ions to form a modified layer in a surface portion of the semiconductor wafer, in which the modified layer includes a constituent element of the cluster ions in solid solution. The production method further includes forming an epitaxial layer on the modified layer of the semiconductor wafer. The irradiating is performed such that a portion of the modified layer in a thickness direction becomes an amorphous layer and an average depth of an amorphous layer surface from a semiconductor wafer surface-side of the amorphous layer is at least 20 nm from the surface of the semiconductor wafer.

Semiconductor epitaxial wafer and method of producing semiconductor epitaxial wafer, and method of producing solid-state imaging device
11935745 · 2024-03-19 · ·

An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1?10.sup.17 atoms/cm.sup.3.

Methods for doping a sub-fin region of a semiconductor structure by backside reveal and associated devices

Methods for doping a sub-fin region of a semiconductor structure include providing a semiconductor structure that comprises a substrate and a plurality of fins formed on the substrate, the plurality of fins having sub-fin regions adjacent to the substrate; removing the substrate to expose a portion of the sub-fin regions of the plurality of fins, and implanting a dopant material into the exposed portion of the sub-fin region. The method may also include performing an annealing process after the implantation such that the dopant becomes electrically active. The method may also include patterning the backside of the semiconductor structure. Devices constructed using the disclosed methods are also provided, and other embodiments are discussed.

Epitaxial wafer manufacturing method and epitaxial wafer

Provided is an epitaxial wafer having an excellent gettering capability and a suppressed formation of epitaxial defects. The epitaxial wafer has a specified resistivity, and includes a modifying layer formed on a surface portion of the silicon wafer and composed of a predetermined element including at least carbon, in the form of a solid solution in the silicon wafer; and an epitaxial layer having a resistivity that is higher than the resistivity of the silicon wafer, wherein a concentration profile of the predetermined element in the modifying layer in a depth direction thereof meets a specified full width half maximum and a specified peak concentration.

Liner planarization-free process flow for fabricating metallic interconnect structures

A method includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening in the dielectric layer. A first layer of metallic material (e.g., non-nitride metal) is deposited to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening. A second layer of metallic material (e.g., copper) is deposited to fill the opening with metallic material. An overburden portion of the second layer of metallic material is removed by planarizing the second layer of metallic material down an overburden portion of the liner layer on the upper surface of the dielectric layer. A surface treatment process (e.g., plasma nitridation) is performed to convert the overburden portion of the liner layer into a layer of metal nitride material. The layer of metal nitride material is selectively etched away using a wet etch process.

LINER PLANARIZATION-FREE PROCESS FLOW FOR FABRICATING METALLIC INTERCONNECT STRUCTURES
20190279873 · 2019-09-12 ·

A method includes forming a dielectric layer on a substrate and patterning the dielectric layer to form an opening in the dielectric layer. A first layer of metallic material (e.g., non-nitride metal) is deposited to form a liner layer on an upper surface of the dielectric layer and on exposed surfaces within the opening. A second layer of metallic material (e.g., copper) is deposited to fill the opening with metallic material. An overburden portion of the second layer of metallic material is removed by planarizing the second layer of metallic material down an overburden portion of the liner layer on the upper surface of the dielectric layer. A surface treatment process (e.g., plasma nitridation) is performed to convert the overburden portion of the liner layer into a layer of metal nitride material. The layer of metal nitride material is selectively etched away using a wet etch process.

METHOD FOR NEUTRAL BEAM PROCESSING BASED ON GAS CLUSTER ION BEAM TECHNOLOGY AND ARTICLES PRODUCED THEREBY

A method for treating a silicon substrate, and a silicon substrate, provide a surface treated with an accelerated neutral beam.

Method and apparatus for neutral beam processing based on gas cluster ion beam technology

An apparatus, method and products thereof provide an accelerated neutral beam derived from an accelerated gas cluster ion beam for processing materials.