H01L21/2658

Semiconductor device with implant and method of manufacturing same

A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 10.sup.19 cm.sup.−3 and about 10.sup.20 cm.sup.−3.

PHOSPHORUS OR ARSENIC ION IMPLANTATION UTILIZING ENHANCED SOURCE TECHNIQUES

Apparatus and method for use of solid dopant phosphorus and arsenic sources and higher order phosphorus or arsenic implant source material are described. In various implementations, solid phosphorus-comprising or arsenic-comprising materials are provided in the ion source chamber for generation of dimer or tetramer implant species. In other implementations, the ion implantation is augmented by use of a reactor for decomposing gaseous phosphorus-comprising or arsenic-comprising materials to form gas phase dimers and tetramers for ion implantation.

Semiconductor device and method of forming the same

A method of forming a semiconductor device includes forming a NMOS gate structure over a substrate. The method further includes forming an amorphized region in the substrate adjacent to the NMOS gate structure. The method also includes forming a lightly doped source/drain (LDD) region in the amorphized region. The method further includes depositing a stress film over the NMOS gate structure, performing an annealing process, and removing the stress film.

Semiconductor device including fin structures and manufacturing method thereof

A method for manufacturing a semiconductor device includes forming a fin structure having a top surface and side surfaces. A mask layer is disposed over the top surface. A doping support layer is formed to cover part of the fin structure. A first impurity is introduced into a first region of the fin structure covered by the doping support layer, by implanting the first impurity into the doping support layer so that the implanted first impurity is introduced into the first region of the fin structure through the side surfaces.

Integration of a memory transistor into high-k, metal gate CMOS process flow

Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method includes: forming a gate stack of a NVM transistor in a NVM region of a substrate including the NVM region and a plurality of MOS regions; and depositing a high-k dielectric material over the gate stack of the NVM transistor and the plurality of MOS regions to concurrently form a blocking dielectric comprising the high-k dielectric material in the gate stack of the NVM transistor and high-k gate dielectrics in the plurality of MOS regions. In one embodiment, a first metal layer is deposited over the high-k dielectric material and patterned to concurrently form a metal gate over the gate stack of the NVM transistor, and a metal gate of a field effect transistor in one of the MOS regions.

Composite impurity scheme for memory technologies

An integrated circuit comprises a memory array including diffusion bit lines having composite impurity profiles in a substrate. A plurality of word lines overlies channel regions in the substrate between the diffusion bit lines, with data storage structures such as floating gate structures or dielectric charge trapping structures, at the cross-points. The composite impurity diffusion bit lines provide source/drain terminals on opposing sides of the channel regions that have high conductivity, good depth and steep doping profiles, even with channel region critical dimensions below 50 nanometers.

Semiconductor device and method of forming the same

A method of forming a semiconductor device includes forming a gate stack over a substrate, forming an amorphized region in the substrate adjacent to an edge of the gate stack, forming a stress film over the substrate, performing a process to form a dislocation with a pinchoff point in the substrate, removing at least a portion of the dislocation to form a recess cavity with a tip in the substrate, and forming a source/drain feature in the recess cavity.

Herbal extracts and flavor systems for oral products and methods of making the same

The invention provides a method for preparing an herbal extract and a flavor system comprising an herbal extract produced by the process. The invention also provides a flavor system comprising an herbal extract comprising thymol, eugenol, carvacrol and eucalyptol. The invention further provides a flavor system comprising a thyme extract having a minimum inhibitory concentration of less than about 3%. Additionally, the invention provides an oral product comprising a flavor system.

DUAL DOPANT SOURCE/DRAIN REGIONS AND METHODS OF FORMING SAME

A method includes forming a source/drain region in a semiconductor fin; after forming the source/drain region, implanting first impurities into the source/drain region; and after implanting the first impurities, implanting second impurities into the source/drain region. The first impurities have a lower formation enthalpy than the second impurities. The method further includes after implanting the second impurities, annealing the source/drain region.

Semiconductor Device with Implant and Method of Manufacturing Same
20230261055 · 2023-08-17 ·

A FinFET is provided including a channel region containing a constituent element and excess atoms, the constituent element belonging to a group of the periodic table of elements, wherein said excess atoms are nitrogen, or belong to said group of the periodic table of elements, and a concentration of said excess atoms in the channel region is in the range between about 1019 cm−3 and about 1020 cm−3.