A memory device that includes a non-volatile memory (NVM) transistor disposed in a first region of a substrate. The NVM transistor includes a first gate including a first type of conductor material. The memory device further includes a first type of low voltage field-effect transistor (LV FET) and an input/out field-effect transistor (I/O FET) disposed in a second region of the substrate. The LV FET includes a second gate comprising a second type of conductor material, the I/O FET includes a third gate comprising a second type of conductor material, and the first and second conductor materials are different. Other embodiments are also described.

The present disclosure provides semiconductor structures. An exemplary semiconductor structure includes a substrate having a first region and a second region; an isolation structure formed in the substrate in the first region; a compensation doping region formed in the substrate in the first region, locate at a side of the isolation structure adjacent to the substrate in the second region and connecting with the isolation structure; a well region formed in the substrate in the second region; a drift region formed in the substrate in the first region and enclosing the isolation structure and the compensation doping region; a gate structure formed over the substrate in a boundary region between the first region and the second region; a source region formed in the well region at one side of the gate structure; and a drain region formed in the drift region at another side of the gate structure.

To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.

An exemplary method includes forming a hard mask layer over an integrated circuit layer and implanting ions into a first portion of the hard mask layer without implanting ions into a second portion of the hard mask layer. An etching characteristic of the first portion is different than an etching characteristic of the second portion. After the implanting, the method includes annealing the hard mask layer. After the annealing, the method includes selectively etching the second portion of the hard mask layer, thereby forming an etching mask from the first portion of the hard mask layer. The method can further include using the etching mask to pattern the integrated circuit layer.

Provided is a method of evaluating the impurity gettering capability of an epitaxial silicon wafer, which allows for very precise evaluation of the impurity gettering behavior of a modified layer formed immediately under an epitaxial layer, the modified layer containing carbon in solid solution. In this method, a modified layer located immediately under an epitaxial layer, the modified layer containing carbon in solid solution, is analyzed by three-dimensional atom probe microscopy, and the impurity gettering capability of the modified layer is evaluated based on a three-dimensional map of carbon in the modified layer, obtained by the analysis.

A method for fabricating a semiconductor device includes receiving a silicon substrate having an isolation feature disposed on the substrate and a well adjacent the isolation feature, wherein the well includes a first dopant. The method also includes etching a recess to remove a portion of the well and epitaxially growing a silicon layer (EPI layer) in the recess to form a channel, wherein the channel includes a second dopant. The method also includes forming a barrier layer between the well and the EPI layer, the barrier layer including at least one of either silicon carbon or silicon oxide. The barrier layer can be formed either before or after the channel. The method further includes forming a gate electrode disposed over the channel and forming a source and drain in the well.

A method and system for fluorine ion implantation is described, where a fluorine compound capable of forming multiple fluorine ionic species is introduced into an ion implanter at a predetermined flow rate. Fluorine ionic species are generated at a predetermined arc power and source magnetic field, providing an optimized beam current for the desired fluorine ionic specie. The desired fluorine ionic specie, such as one having multiple fluorine atoms, is implanted into the substrate under the selected operating conditions.

A system and method for fluorine ion implantation is described, which includes a fluorine gas source used to generate a fluorine ion species for implantation to a subject, and an arc chamber that includes one or more non-tungsten materials (graphite, carbide, fluoride, nitride, oxide, ceramic). The system minimizes formation of tungsten fluoride during system operation, thereby extending source life and promoting improved system performance. Further, the system can include a hydrogen and/or hydride gas source, and these gases can be used along with the fluorine gas to improve source lifetime and/or beam current.

A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

One embodiment of the invention relates to a method for fabricating a doped semiconductor zone in a semiconductor body. The method includes implanting dopant particles via one side into the semiconductor body or applying a layer containing dopant particles to one side of the semiconductor body. The method also includes irradiating the semiconductor body via the one side with further particles at least in the region containing the dopant particles. The method finally includes carrying out a thermal treatment by means of which the semiconductor body is heated, at least in the region containing the dopant particles, to a predetermined temperature in order to activate the implanted dopant particles, said temperature being less than 700 C.