The present disclosure provides semiconductor structures. An exemplary semiconductor structure includes a substrate having a first region and a second region; an isolation structure formed in the substrate in the first region; a compensation doping region formed in the substrate in the first region, locate at a side of the isolation structure adjacent to the substrate in the second region and connecting with the isolation structure; a well region formed in the substrate in the second region; a drift region formed in the substrate in the first region and enclosing the isolation structure and the compensation doping region; a gate structure formed over the substrate in a boundary region between the first region and the second region; a source region formed in the well region at one side of the gate structure; and a drain region formed in the drift region at another side of the gate structure.

Provided is a manufacturing method for a semiconductor device including a transistor portion and a diode portion. The manufacturing method includes forming, on an upper surface of a semiconductor substrate including a bulk donor, an emitter region of the transistor portion and an anode region of the diode portion as an active region, performing ion implantation of a first dopant of a first conductivity type to the transistor portion and the diode portion from a lower surface of the semiconductor substrate, and performing ion implantation of a second dopant of the first conductivity type to the transistor portion from the lower surface of the semiconductor substrate.

Tunnel field effect devices and methods of fabricating tunnel field effect devices are described. In one embodiment, the semiconductor device includes a first drain region of a first conductivity type disposed in a first region of a substrate, a first source region of a second conductivity type disposed in the substrate, the second conductivity type being opposite the first conductivity type, a first channel region electrically coupled between the first source region and the first drain region, the first source region underlying a least a portion of the first channel region, and a first gate stack overlying the first channel region.

The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a substrate having a first region and a second region; forming a trench in the substrate in the first region; forming a compensation doping region in a side surface of the trench adjacent to the second region; forming an isolation structure in the trench; forming a well region in the substrate in the second region; forming a drift region in the substrate in the first region; forming a gate structure over the substrate in a boundary region between the first region and the second region, and covering a portion of the isolation structure; and forming a source region in the well region at one side of the gate structure and a drain region in the drift region at another side of the gate structure.

A semiconductor device is produced by providing a semiconductor substrate, forming an epitaxial layer on the semiconductor substrate, and introducing dopant atoms of a first doping type and dopant atoms of a second doping type into the epitaxial layer.

A semiconductor device includes a channel region comprising dopants, a gate structure over the channel region and a deactivated region underneath the gate structure and partially within the channel region. Dopants within the deactivated region are deactivated. The deactivated region includes carbon. The deactivated region is physically separated from a top surface of a substrate by a portion of the substrate that is free of carbon.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

To manufacture an integrated circuit device, a diffusion buffer layer and a carbon-containing layer are sequentially formed on a plurality of fin-type active regions formed in a substrate. A carbon-containing mask pattern is formed to have an opening exposing a portion of the diffusion buffer layer by etching the carbon-containing layer using an etching gas including an oxygen atom while the diffusion buffer layer is blocking oxygen from diffusing into the fin-type active regions. Impurity ions are implanted into some fin-type active regions through the opening and the diffusion buffer layer using the carbon-containing mask pattern as an ion-implantation mask, the some fin-type active regions being selected from among the plurality of fin-type active regions.

Apparatus and method for use of solid dopant phosphorus and arsenic sources and higher order phosphorus or arsenic implant source material are described. In various implementations, solid phosphorus-comprising or arsenic-comprising materials are provided in the ion source chamber for generation of dimer or tetramer implant species. In other implementations, the ion implantation is augmented by use of a reactor for decomposing gaseous phosphor-us-comprising or arsenic-comprising materials to form gas phase dimers and tetramers for ion implantation.

A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.