The present disclosure provides a fabrication method that includes providing a workpiece having a semiconductor substrate that includes a first circuit area and a second circuit area; forming a first active region in the first circuit area and a second active region on the second circuit area; forming first stacks with a first gate spacing on the first active region and second gate stacks with a second gate spacing on the second active region, the second gate spacing being different from the first gate spacing; performing an ion implantation to introduce a doping species to the first active region; performing an etching process, thereby recessing both first source/drain regions of the first active region with a first etch rate and second source/drain regions of the second active region; and epitaxially growing first source/drain features within the first source/drain regions and second source/drain features within the second source/drain regions.

A semiconductor manufacturing apparatus according to the present embodiment includes a stage on which a wafer can be placed. A separator separates a beam of impurities to be introduced into the wafer into an ion component and a neutral component. A controller switches the semiconductor manufacturing apparatus between a first mode and a second mode, where in the first mode, the ion component is introduced into the wafer and in the second mode, the neutral component is introduced into the wafer.

A semiconductor device has a substrate made of a first semiconductor material. The first semiconductor material is silicon carbide. A first semiconductor layer made of the first semiconductor material is disposed over the substrate. A second semiconductor layer made of a second semiconductor material dissimilar from the first semiconductor material is disposed over the first semiconductor layer. The first semiconductor material is substantially defect-free silicon carbide, and the second semiconductor material is silicon. A semiconductor device is formed in the second semiconductor layer. The semiconductor device can be a power MOSFET, diode, insulated gate bipolar transistor, cluster trench insulated gate bipolar transistor, and thyristor. The second semiconductor layer with the electrical component provides a first portion of a breakdown voltage for the semiconductor device and the first semiconductor layer and substrate provide a second portion of the breakdown voltage for the semiconductor device.

A semiconductor device includes: a first stacked structure including a first lower dielectric layer, a first horizontal gate structure, and a first upper dielectric layer stacked vertically; a second stacked structure including a second lower dielectric layer, a second horizontal gate structure, and a second upper dielectric layer stacked vertically, and having a first side facing a first side of the first stacked structure; a first channel layer formed on the first side of the first stacked structure; a second channel layer formed on the first side of the second stacked structure; a lower electrode layer commonly coupled to lower ends of the first and second channel layers between the first and second stacked structures; a first upper electrode layer coupled to an upper end of the first channel layer; and a second upper electrode layer coupled to an upper end of the second channel layer.

A method for forming a semiconductor device involves providing a semiconductor wafer having an active layer of a first conductivity type. First and second gates having first and second gate polysilicon are formed on the active layer. A first mask region is formed on the active layer. Between the first and second gates, using the first mask region, the first gate polysilicon, and the second gate polysilicon as a mask, a deep well of a second conductivity type, a shallow well of the second conductivity type, a source region of the first conductivity type, and first and second channel regions of the second conductivity type, are formed. In the active layer, using one or more second mask regions, first and second drift regions of the first conductivity type, first and second drain regions of the first conductivity type, and a source connection region of the second conductivity type, are formed.

A semiconductor structure and a method for forming a semiconductor structure are provided. In some embodiments, a method is provided. The method includes following operations. A sacrificial gate structure is formed over a fin structure. The sacrificial gate structure includes a sacrificial gate layer and a sacrificial dielectric layer. The sacrificial gate layer is removed to form a gate trench exposing the sacrificial dielectric layer. A doped region is formed in the fi structure covered by the sacrificial dielectric layer. The sacrificial dielectric layer, a portion of the doped region and a portion of the fin structure are removed from the gate trench. An interfacial layer is formed over the fin structure in the gate trench.

A multi-finger transistor structure is provided in the present invention, including multiple active areas, a gate structure consisting of multiple gate parts and connecting parts, wherein each gate part crosses over one of the active areas and each connecting part alternatively connects one end and the other end of the gate parts so as to form a meander gate structure, and multiple sources and drains, wherein one source and one drain are set between two adjacent gate parts, and each gate parts is accompanied by one source and one drain at two sides respectively, and the distance between the drain and the gate part is larger than the distance between the source and the gate part, so that the source and the drain are asymmetric with respect to the corresponding gate part, and air gaps are formed in the dielectric layer between each drain and the corresponding gate part.

A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.

A semiconductor device has a first substrate and a first semiconductor layer having a first semiconductor material formed over the first substrate. A surface of the first semiconductor layer has a first element of the first semiconductor material. A first surface of a second semiconductor layer having the first semiconductor material is joined to the surface of the first semiconductor layer. The first surface of the second semiconductor layer has a second element of the first semiconductor material different from the first element. The first semiconductor material is silicon carbide or cubic silicon carbide. The first element is silicon or carbon, and the second element is carbon or silicon. The semiconductor device provides characteristics of radiation hardening. A third semiconductor layer is formed over a second surface of the second semiconductor layer opposite the first surface. An electrical component is formed over the second semiconductor layer.

In a general aspect, a vertical transistor can include a semiconductor region of a first conductivity type, and a plurality of perpendicularly intersecting trenches having a shielded gate structure of the vertical transistor disposed therein. A mesa of the semiconductor region can be defined by the plurality of perpendicularly intersecting trenches. The mesa can include a proximal end portion having a first doping concentration of the first conductivity type, a distal end portion having the first doping concentration of the first conductivity type, and a central portion disposed between the proximal end portion and the distal end portion. The central portion can have a second doping concentration of the first conductivity type that is less than the first doping concentration.