Halogen lamps arranged in two, upper and lower, tiers to intersect each other in a lattice pattern are provided under a chamber for receiving a semiconductor wafer therein. In a location where the halogen lamps in the upper and lower tiers overlap each other, a reflector is provided such that an outer wall surface of a glass tube of each halogen lamp is open on upper and lower sides. In the location where the halogen lamps in the upper and lower tiers overlap each other, light emitted upwardly from a halogen lamp in the lower tier is transmitted through the open upper and lower portions of the outer wall surface of the glass tube of a halogen lamp in the upper tier, and is directed further upwardly. Thus, the light is prevented from entering the glass tube of the halogen lamp in the lower tier again.

A resistive element in an artificial neural network, the resistive element includes a Silicon-on-insulator (SOI) substrate, and a Silicon layer formed on the Silicon-on-insulator substrate. The Silicon layer includes dopants derived from a thin film dopant layer, and the thin film dopant layer includes a programmed amount of dopant including at least one of Boron and Phosphorus.

Methods and systems for implementing artificial intelligence enabled preparation end-pointing are disclosed. An example method at least includes obtaining an image of a surface of a sample, the sample including a plurality of features, analyzing the image to determine whether an end point has been reached, the end point based on a feature of interest out of the plurality of features observable in the image, and based on the end point not being reached, removing a layer of material from the surface of the sample.

The present disclosure provides a wafer annealing method, including: preparing a wafer, the wafer includes a plurality of regions concentrically disposed on the wafer; heating the plurality of regions, the heating process includes a plurality of heating stages, each of the heating stages has a different heating rate, temperatures of the plurality of regions vary in each of the heating stages; performing heat preservation on the plurality of regions; and cooling the plurality of regions through blowing nitrogen. The wafer annealing method can improve the electrical uniformity of the wafer.

Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula In.sub.xAl.sub.yGa.sub.1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm.sup.−1 or more and 4.6 cm.sup.−1 or less under a temperature condition of normal temperature.

A susceptor for semiconductor substrate processing is disclosed herein. In some embodiments, the susceptor may comprise an inner susceptor portion and an outer susceptor portion. The susceptor portions may self-align via complementary features, such as tabs on the outer susceptor and recesses on the inner susceptor portion. The inner susceptor portion may contain several contact pads with which to support a wafer during semiconductor processing. In some embodiments, the contact pads are hemispherical to reduce contact area with the wafer, thereby reducing risk of backside damage. The inner susceptor portion may contain a cavity with which to receive a thermocouple. In some embodiments, the diameter of the cavity is greater than the diameter of the thermocouple such that the thermocouple does not contact the walls of the cavity during processing, thereby providing highly accurate temperature measurements.

A heating treatment method includes: a step (A) of supplying power to both a heating lamp and an LED, and irradiating a heating object with light emitted from the heating lamp and light emitted from the LED to raise the temperature of the heating object; a step (B) of decreasing the power supplied to the heating lamp after performing the step (A); and a step (C) of lowering the temperature of the heating object by decreasing the power supplied to the LED after performing the step (B).

A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer.

Multiple theoretical reflectances determined by simulation for a silicon substrate with thin films of multiple types and thicknesses formed thereon are registered in association with the types and the thicknesses in a database. A carrier storing semiconductor wafers in a lot is transported into a heat treatment apparatus. A reflectance of a semiconductor wafer is measured by applying light to a surface of the semiconductor wafer. The theoretical reflectance of the semiconductor wafer is calculated from the measured reflectance thereof. A theoretical reflectance closely resembling the theoretical reflectance of the semiconductor wafer is extracted from among the multiple theoretical reflectances registered in the database, whereby the type and thickness of the thin film formed on the surface of the semiconductor wafer are specified. Treatment conditions for the semiconductor wafer are determined based on the specified type and thickness of the thin film.