The semiconductor device includes a mesa diode structure(20) and a protective layer(17b). The mesa diode structure includes, from bottom to top, a P-type semiconductor layer(11), a first N-type semiconductor layer(12), and a second N-type semiconductor layer(13) having a higher impurity concentration than the first N-type semiconductor layer. The protective layer is arranged on a side wall around the mesa diode structure seen in a plane. Specifically, the protective layer is arranged on an upper side surface(11c) of the P-type semiconductor layer and on side surfaces(12a,13a) of the first N-type semiconductor layer and the second N-type semiconductor layer, but is not arranged on a lower side surface of the P-type semiconductor layer. A bevel angle(30) of a PN junction plane between the P-type semiconductor layer and the first N-type semiconductor layer to the upper side surface of the P-type semiconductor layer is set to 85 to 120 degrees.

Techniques and mechanisms for high interconnect density communication with an interposer. In some embodiments, an interposer comprises a substrate and portions disposed thereon, wherein respective inorganic dielectrics of said portions adjoin each other at a material interface, which extends to each of the substrate and a first side of the interposer. A first hardware interface of the interposer spans the material interface at the first side, wherein a first one of said portions comprises first interconnects which couple the first hardware interface to a second hardware interface at the first side. A second one of said portions includes second interconnects which couple one of first hardware interface or the second hardware interface to a third hardware interface at another side of the interposer. In another embodiment, a metallization pitch feature of the first hardware interface is smaller than a corresponding metallization pitch feature of the second hardware interface.

A processing method for processing a single-crystal silicon wafer that has a first surface and a second surface formed in such a manner that a specific crystal plane included in a crystal plane {100} is exposed in each of the first and second surfaces and has devices formed in the respective regions marked out by planned dividing lines in the first surface. The method includes forming dividing origins along each planned dividing line, forming a separation layer along the crystal plane of the second surface through relatively moving a focal point and the wafer along a first direction that is parallel to the crystal plane of the second surface and in which an acute angle formed between the first direction and the crystal orientation <100> is equal to or smaller than 5°, and separating the wafer into a first-surface-side wafer including devices and a second-surface-side wafer including no devices.

A processing method for a wafer having a chamfered portion at a peripheral edge includes a holding step of holding the wafer by a holding table, and a chamfer removing step of rotating the holding table while causing a first cutting blade to cut into the peripheral edge of the wafer while supplying a cutting liquid from a first cutting liquid supply nozzle to cut the peripheral edge of the wafer. In the chamfer removing step, a second cutting unit is positioned at a position adjacent to the first cutting unit at such a height that a second cutting blade does not make contact with the wafer and on the side of the center of the wafer as compared to the first cutting unit, and the cutting liquid is supplied from a second cutting liquid supply nozzle.

A sheet for thermal bonding which has a tensile modulus of 10 to 3,000 MPa and contains fine metal particles in an amount in the range of 60-98 wt % and which, when heated from 23° C. to 400° C. in the air at a heating rate of 10° C./min and then examined by energy dispersive X-ray spectrometry, has a carbon concentration of 15 wt % or less.

There is provided a cutting method for cutting a processing-target object by a cutting blade. The cutting method includes a holding step of holding the processing-target object by a holding table and a cutting step of cutting the processing-target object by the cutting blade by causing the cutting blade that rotates to cut into the processing-target object held by the holding table and causing the holding table and the cutting blade to relatively move after the holding step is carried out. In the cutting step, cutting is carried out with detection of whether or not a crack in the processing-target object exists by a crack detecting unit disposed on the rear side relative to the cutting blade in a cutting progression direction in which cutting processing of the processing-target object by the cutting blade progresses.

A wafer structure and a trimming method thereof are provided. The wafer structure includes a first wafer which includes a front surface, a back surface, and a sidewall connected to the front surface and the back surface. The sidewall of the first wafer includes a plurality of first regions at an edge of the sidewall and the back surface and laterally separated from one another by a pitch. Each of the first regions extends from the back surface toward the front surface and has etching streaks thereon.

A method for manufacturing a semiconductor device includes forming a first stacked body having a plurality of first material films and a plurality of second material films that are alternately stacked, in a divided region of a semiconductor wafer including a chip region in which a semiconductor element is provided and the divided region between the adjacent chip regions, a plurality of times in a normal line direction of a substrate surface of the semiconductor wafer. The semiconductor wafer is fragmented by a blade having a width wider than the width of the first stacked body.

A protective sheeting for use in processing a semiconductor-sized wafer includes a protective film and a cushioning layer attached to a back surface of the protective film. At least in a central area of the protective sheeting, no adhesive is applied to a front surface and a back surface of the protective sheeting, the central area having an outer diameter which is equal to or larger than an outer diameter of the semiconductor-sized wafer. Further, a protective sheeting for use in processing a wafer has a protective film and a cushioning layer attached to a back surface of the protective film, wherein, on an entire front surface and an entire back surface of the protective sheeting, no adhesive is applied. A handling system for a semiconductor-sized wafer and to a combination of a wafer and the protective sheeting are also described.

A wafer structure and a trimming method thereof are provided. The wafer structure includes a first wafer which includes a front surface, a back surface, and a sidewall connected to the front surface and the back surface. The sidewall of the first wafer includes a plurality of first regions at an edge of the sidewall and the back surface and laterally separated from one another by a pitch. Each of the first regions extends from the back surface toward the front surface and has etching streaks thereon.