Methods and improved process flows are provided herein for forming self-aligned contacts using spin-on silicon carbide (SiC). More specifically, the disclosed methods and process flows form self-aligned contacts by using spin-on SiC as a cap layer for at least one other structure, instead of depositing a SiC layer via plasma vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. The other structure may be a source and drain contact made through the use of a trench conductor. By utilizing spin-on SiC as a cap layer material, the disclosed methods and process flows avoid problems that typically occur when SiC is deposited, for example by CVD, and subsequently planarized. As such, the disclosed methods and process flows improve upon conventional methods and process flows for forming self-aligned contacts by reducing defectivity and improving yield.

A method of shaping a surface comprises dispensing formable material onto a substrate held by a substrate chuck, contacting a plate held by a plate chuck assembly with the formable material to form a film, curing the film to form a cured layer, initiating a separation front between the cured layer and the plate, tilting the plate chuck assembly and/or the substrate chuck in a direction away from the initial separation point, thereby propagating the separation front, applying a force to the plate chuck assembly and/or the substrate chuck away from the other while maintaining or increasing the tilt, until the separation front completely propagates around the cured layer, and continuing to apply the force, until the plate does not contact the cured layer. The plate chuck assembly includes a flexible portion with a central opening, and a cavity formed by the flexible portion. The plate is held by the flexible portion.

A planarization system comprises a substrate chuck configured to hold a substrate, a superstrate chuck configured to hold a superstrate, a planarizing head configured to support the superstrate chuck, a positioning system configured to cause the superstrate to come into contact with formable material dispensed on the substrate to form a multilayer structure, the multilayer structure including the superstrate, a film of the formable material, and the substrate, and an annular light source disposed between an upper end of the planarizing head and the substrate chuck. The annular light source is configured to emit light onto an outer annular region of the multilayer structure without emitting the light onto an inner central region of the multilayer structure. The inner central region is located radially inward relative to the outer annular region.

The present disclosure provides a semiconductor device structure with a conductive contact and a method for preparing the semiconductor device structure. The semiconductor device structure includes a dielectric layer disposed over a semiconductor substrate; a conductive contact penetrating through the dielectric layer; and a metal oxide layer separating the conductive contact from the dielectric layer, wherein the conductive contact and the metal oxide layer comprise a same metal.

A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate. The first and second fin structures have respective first and second vertical dimensions that are about equal to each other. The method further includes modifying the first fin structure such that the first vertical dimension of the first fin structure is smaller than the second vertical dimension of the second fin structure and depositing a dielectric layer on the modified first fin structure and the second fin structure. The method further includes forming a polysilicon structure on the dielectric layer and selectively forming a spacer on a sidewall of the polysilicon structure.

Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.

A laser structure may include a substrate, an active region arranged on the substrate, and a waveguide arranged on the active region. The waveguide may include a first surface and a second surface that join to form a first angle relative to the active region. A material may be deposited on the first surface and the second surface of the waveguide.

A substrate polishing apparatus includes a polishing table 30 having a polishing surface 10 in the upper surface, a substrate holding portion 31 that holds a substrate W having a surface to be polished in the lower surface, and a holding portion cover 36 that covers the outer side of the substrate holding portion 31. Between the lower portion of the holding portion cover 36 and the upper surface of the polishing table 30, a gap portion for intake 37 is provided, and in the upper portion of the holding portion cover 36, a pipe for exhaust 39 connected to an exhaust mechanism 38 is provided. By operating the exhaust mechanism 38, a rising air current from the gap portion 37 toward the pipe 39 is formed between the outer surface of the substrate holding portion 31 and the inner surface of the holding portion cover 36.

The present disclosure provides a method for manufacturing a semiconductor device, including: providing a substrate having a plurality of stacked gates with silicon nitride mask layer and silicon oxide mask layer formed on top of the surface; depositing a first carbon-containing silicon oxide thin layer; depositing a second non-carbon-containing silicon oxide layer to fill the gaps between adjacent stacked gates; and planarizing the first silicon oxide thin layer and the second silicon oxide layer by applying the silicon nitride mask layer as a stop layer, removing the second silicon oxide layer, and forming the first sidewalls with the first silicon oxide thin layer on the sides of the stacked gates. The present disclosure further provides a semiconductor device made with the method thereof. The present disclosure can remove the silicon oxide mask layer above the stacked gates through a simple process flow.

Non-planar semiconductor devices having doped sub-fin regions and methods of fabricating non-planar semiconductor devices having doped sub-fin regions are described. For example, a method of fabricating a semiconductor structure involves forming a plurality of semiconductor fins above a semiconductor substrate. A solid state dopant source layer is formed above the semiconductor substrate, conformal with the plurality of semiconductor fins. A dielectric layer is formed above the solid state dopant source layer. The dielectric layer and the solid state dopant source layer are recessed to approximately a same level below a top surface of the plurality of semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins. The method also involves driving dopants from the solid state dopant source layer into the sub-fin regions of each of the plurality of semiconductor fins.