In a method of manufacturing a semiconductor device, a sacrificial gate structure including sacrificial gate electrode is formed over a substrate. A first dielectric layer is formed over the sacrificial gate structure. A second dielectric layer is formed over the first dielectric layer. The second and first dielectric layers are planarized and recessed, and an upper portion of the sacrificial gate structure is exposed. A third dielectric layer is formed over the exposed sacrificial gate structure and over the first dielectric layer. A fourth dielectric layer is formed over the third dielectric layer. The fourth and third dielectric layers are planarized, and the sacrificial gate electrode is exposed and part of the third dielectric layer remains on the recessed first dielectric layer. The recessing the first dielectric layer comprises a first etching operation and a second etching operation using a different etching as from the first etching operation.

A method for forming an SOI substrate is provided. The method includes following operations. A recycle substrate is received. A first multilayered structure is formed on the recycle substrate. A trench is formed in the first multilayered structure. A lateral etching is performed to remove portions of sidewalls of the trench to form a recess in the first multilayered structure. The trench and the recess are sealed with an epitaxial layer, and a potential cracking interface is formed in the first multilayered structure. A second multilayered structure is formed over the first multilayered structure. The device layer of the recycle substrate is bonded to an insulator layer over an carrier substrate. The first multilayered structure is cleaved along the potential cracking interface to separate the recycle substrate from the second multilayered structure, the insulator layer and the carrier substrate. The device layer is exposed.

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, first and second fin structures formed over the substrate, and an isolation structure between the first and second fin structures. The isolation structure can include a lower portion and an upper portion. The lower portion of the isolation structure can include a metal-free dielectric material. The upper portion of the isolation structure can include a metallic element and silicon.

A method for forming a planarization layer includes: providing a substrate including a trench; coating a pre-thinner over a surface of the trench; forming a gap-filling material in the trench; coating a post-thinner over the gap-filling material; and performing a spinning process to rotate the substrate.

A planarization system is provided. The planarization system includes a first substrate chuck which holds the substrate during a planarization step, and a second substrate chuck which holds the substrate with a non-flat configuration during a separation step.

A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO.sub.2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO.sub.2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.

A set of silicon fins for n-type FinFET devices and a set of silicon germanium fins for p-type FinFET devices are provided on a strain relaxation buffer (SRB) substrate. Each fin in the set of silicon fins is cut forming a set of cut silicon fins having a set of vertical faces at a fin end of a respective cut silicon fin. Each fin in the set of silicon germanium fins is cut forming a set of cut silicon germanium fins having a set of vertical faces at a fin end of a respective silicon germanium fin. A set of tensile dielectric structures is formed. Each of the tensile dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon fins to maintain tensile strain at the fin ends of the set of cut silicon fins. A set of compressive dielectric structures are formed. Each of the compressive dielectric structures respectively contact the vertical faces of respective fin ends of the cut silicon germanium fins to maintain compressive strain at the fin ends of the set of cut silicon fins. Another aspect of the invention is a device which is created by the method.

A method of manufacturing a semiconductor device is provided. The semiconductor device includes a semiconductor substrate, first and second fins on the semiconductor substrate and separated by a trench. The first fin includes a first portion having a first conductivity type and a second portion having a second conductivity type different from the first conductivity type, the first and second portions are adjacent to each other, and the second portion connected to the second fin through the semiconductor substrate. The semiconductor device also includes a gate structure on the first and second portions and including a gate insulator layer on the first and second portions, a gate on a portion of the gate insulator layer on the first portion, and a dummy gate on the second portion and including an insulating layer or an undoped semiconductor layer and adjacent to the gate.

A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

An apparatus includes a first substrate chuck configured to hold a first substrate, a second substrate chuck configured to hold a second substrate, and a dispenser configured to dispense a formable material onto the first substrate while the first substrate overlies the first substrate chuck and to dispensing the formable material onto the second substrate while the second substrate overlies the second substrate chuck. A method of forming a planarization layer on a substrate can use the apparatus. A method of making an article can include the method of forming the planarization layer.