An etching method includes: (a) providing a substrate including a silicon-containing film on a substrate support; (b) adjusting a temperature of the substrate support to −20° C. or lower; (c) supplying a processing gas including a nitrogen-containing gas, into the chamber; (d) etching the silicon-containing film by using plasma generated from the processing gas. A recess is formed by etching the silicon-containing film, and a by-product containing silicon and nitrogen adheres to a side wall of the recess. The etching method further includes (e) setting at least one etching parameter of the temperature of the substrate support and the flow rate of the nitrogen-containing gas included in the processing gas, to adjust the width of the bottom of the recess according to an adhesion amount of the by-product, before (b).

A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

A semiconductor device may include active patterns extended in a first direction and spaced apart from each other in the first direction, a device isolation layer defining the active patterns, an insulating structure provided between the active patterns and between the device isolation layer, and a gate structure disposed on the insulating structure and extended in a second direction crossing the first direction. The gate structure may include an upper portion and a lower portion. The lower portion of the gate structure may be enclosed by the insulating structure.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

A resist underlayer film composition for use in a multilayer resist method, containing one or more compounds shown by formula (1), and an organic solvent,

WX).sub.n   (1)

W represents an n-valent organic group having 2 to 50 carbon atoms. X represents a monovalent organic group shown by formula (1X). “n” represents an integer of 1 to 10,

##STR00001##

The dotted line represents a bonding arm. R.sup.01 represents an acryloyl or methacryloyl group. Y represents a single bond or a carbonyl group. Z represents a monovalent organic group having 1 to 30 carbon atoms. A resist underlayer film composition can be cured by high energy beam irradiation and form a resist underlayer film having excellent filling and planarizing properties and appropriate etching resistance and optical characteristics in a fine patterning process by a multilayer resist method in the semiconductor apparatus manufacturing process.

A resist underlayer film composition for use in a multilayer resist method, containing one or more compounds shown by formula (1), and an organic solvent,

WX).sub.n   (1)

W represents an n-valent organic group having 2 to 50 carbon atoms. X represents a monovalent organic group shown by formula (1X). “n” represents an integer of 1 to 10,

##STR00001##

The dotted line represents a bonding arm. R.sup.01 represents an acryloyl or methacryloyl group. Y represents a single bond or a carbonyl group. Z represents a monovalent organic group having 1 to 30 carbon atoms. A resist underlayer film composition can be cured by high energy beam irradiation and form a resist underlayer film having excellent filling and planarizing properties and appropriate etching resistance and optical characteristics in a fine patterning process by a multilayer resist method in the semiconductor apparatus manufacturing process.

A semiconductor fabrication apparatus includes a source chamber being operable to generate charged particles; and a processing chamber integrated with the source chamber and configured to receive the charged particles from the source chamber. The processing chamber includes a wafer stage being operable to secure and move a wafer, and a laser-charged particles interaction module that further includes a laser source to generate a first laser beam; a beam splitter configured to split the first laser beam into a second laser beam and a third laser beam; and a mirror configured to reflect the third laser beam such that the third laser beam is redirected to intersect with the second laser beam to form a laser interference pattern at a path of the charged particles, and wherein the laser interference pattern modulates the charged particles by in a micron-zone mode for processing the wafer using the modulated charged particles.

The present invention is related to a method for fabricating a semiconductor device capable of forming fine patterns. The method for fabricating the semiconductor device according to the present invention may comprise forming an etch mask layer on an etch target layer; forming a spacer structure in which first spacers and second spacers are alternately disposed and spaced apart from each other on the etch mask layer; forming first spacer lines through selective etching of the first spacers; forming second spacer lines through selective etching of the second spacers; and etching the etch target layer to form a plurality of fine line patterns using the first and second spacer lines.

Various embodiments of the present disclosure are directed towards a method for forming a bipolar junction transistor (BJT). A dielectric film is deposited over a substrate and comprises a lower dielectric layer, an upper dielectric layer, and an intermediate dielectric layer between the lower and upper dielectric layers. A first semiconductor layer is deposited over the dielectric film and is subsequently patterned to form an opening exposing the dielectric film. A first etch is performed into the upper dielectric layer through the opening to extend the opening to the intermediate dielectric layer. Further, the first etch stops on the intermediate dielectric layer and laterally undercuts the first semiconductor layer. Additional etches are performed to extend the opening to the substrate. A lower base structure and an emitter are formed stacked in and filling the opening, and the first semiconductor layer is patterned to form an upper base structure.

Trenches of different depths in an integrated circuit are formed by a process utilizes a dry etch. A first stop layer is formed over first and second zones of the substrate. A second stop layer is formed over the first stop layer in only the second zone. A patterned mask defines the locations where the trenches are to be formed. The dry etch uses the mask to etch in the first zone, in a given time, through the first stop layer and then into the substrate down to a first depth to form a first trench. This etch also, at the same time, etch in the second zone through the second stop layer, and further through the first stop layer, and then into the substrate down to a second depth to form a second trench. The second depth is shallower than the first depth.