An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.

An integrated circuit product includes a first layer of insulating material including a first insulating material. The first layer of insulating material is positioned above a device layer of a semiconductor substrate. The first layer of insulating material has a lowermost surface positioned above an uppermost surface of a gate of a transistor in a device layer of a semiconductor substrate. The device layer includes transistors. A metallization blocking structure is positioned in an opening in the first layer of insulating material. The metallization blocking structure has a lowermost surface above the uppermost surface of the gate and includes a second insulating material that is different from the first insulating material. The metallization blocking structure includes a second insulating material that is different from the first insulating material. A metallization trench is defined in the first layer of insulating material on opposite sides of the metallization blocking structure. A conductive metallization line includes first and second portions positioned in the metallization trench on opposite sides of the metallization blocking structure. The conductive metallization line has a long axis extending along the first and second portions.

Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.

The disclosed technology generally relates to forming a titanium nitride-based thin films, and more particularly to a conformal and smooth titanium nitride-based thin films and methods of forming the same. In one aspect, a method of forming a thin film comprising one or both of TiSiN or TiAlN comprises exposing a semiconductor substrate to one or more vapor deposition cycles at a pressure in a reaction chamber greater than 1 torr, wherein a plurality of the vapor deposition cycles comprises an exposure to a titanium (Ti) precursor, an exposure to a nitrogen (N) precursor and an exposure to one or both of a silicon (Si) precursor or an aluminum (Al) precursor.

A method comprises depositing a barrier layer on a dielectric layer to prevent oxidation of a metal layer to be deposited by electroplating due to an oxide present in the dielectric layer and depositing a doped liner layer on the barrier layer to bond with the metal layer to be deposited on the liner layer by the electroplating. The dopant forms a protective passivation layer on a surface of the liner layer and dissolves during the electroplating so that the metal layer deposited on the liner layer by the electroplating bonds with the liner layer. The dopant reacts with the dielectric layer and forms a layer of a compound between the barrier layer and the dielectric layer. The compound layer prevents oxidation of the barrier layer and the liner layer due to the oxide present in the dielectric layer and adheres the barrier layer to the dielectric layer.

Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises an interlayer dielectric (ILD) layer disposed over a substrate; a first conductive feature at least partially embedded in the ILD layer; a dielectric layer disposed over and aligned with the ILD layer, wherein a top surface of the dielectric layer is above a top surface of the first conductive feature; an etch stop layer (ESL) disposed over the dielectric layer and over the first conductive feature; and a second conductive feature disposed on the first conductive feature, wherein the second conductive feature includes a first portion having a first bottom surface contacting a top surface of the first conductive feature and a second portion having a second bottom surface contacting a top surface of the dielectric layer.

Process chamber lid assemblies and process chambers comprising same are described. The lid assembly has a housing with a gas dispersion channel in fluid communication with a lid plate. A contoured bottom surface of the lid plate defines a gap to a top surface of a gas distribution plate. A pumping channel is formed between an upper outer peripheral contour of the gas distribution plate and the lid plate.