Methods and apparatus for selectively depositing a titanium material layer atop a substrate having a silicon surface and a dielectric surface are disclosed. In embodiments an apparatus is configured for forming a remote plasma reaction between titanium tetrachloride (TiCl.sub.4), hydrogen (H.sub.2) and argon (Ar) in a region between a lid heater and a showerhead of a process chamber at a first temperature of 200 to 800 degrees Celsius; and flowing reaction products into the process chamber to selectively form a titanium material layer upon the silicon surface of the substrate.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

A method of fabricating a semiconductor integrated circuit (IC) is disclosed. A first conductive feature and a second conductive feature are provided. A first hard mask (HM) is formed on the first conductive feature. A patterned dielectric layer is formed over the first and the second conductive features, with first openings to expose the second conductive features. A first metal plug is formed in the first opening to contact the second conductive features. A second HM is formed on the first metal plugs and another patterned dielectric layer is formed over the substrate, with second openings to expose a subset of the first metal plugs and the first conductive features. A second metal plug is formed in the second openings.

An integrated circuit and method comprising an underlying metal geometry, a dielectric layer on the underlying metal geometry, a contact opening through the dielectric layer, an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening, and an oxidation resistant barrier layer disposed between the underlying metal geometry and overlying metal geometry. The oxidation resistant barrier layer is formed of TaN or TiN with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm.

In one example, an electroplating system comprises a bath reservoir, a holding device, an anode, a direct current power supply, and a controller. The bath reservoir contains an electrolyte solution. The holding device holds a wafer submerged in the electrolyte solution. The wafer comprises features covered by a cobalt layer. The anode is opposite to the wafer and submerged in the electrolyte solution. The direct current power supply generates a direct current between the holding device and the anode. A combination of forward and reverse pulses is applied between the holding device and the anode to electroplate a copper layer on the cobalt layer of the wafer.

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

An interconnect structure and a method of forming the interconnect structure are provided. A dielectric layer and openings therein are formed over a substrate. A conductive seed layer is formed over the top surface and along a bottom and sidewalls of the openings. A conductive fill layer is formed over the seed layer. Metal oxide on the surface of the seed layer may be reduced/removed by a surface pre-treatment. The cleaned surface is covered by depositing fill material over the seed layer without exposing the surface to oxygen. The surface treatment may include a reactive remote plasma clean using hydrogen radicals. If electroplating is used to deposit the fill layer, then the surface treatment may include soaking the substrate in the electrolyte before turning on the electroplating current. Other surface treatments may include active pre-clean (APC) using hydrogen radicals; or Ar sputtering using a metal clean version xT (MCxT) tool.

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

Provided is a method of depositing tungsten, in which depositing a tungsten nucleation layer is formed by performing a unit cycle at least once, wherein the unit cycle includes an absorption step in which a first process gas is provided on a substrate such that at least a portion of the first process gas is absorbed on the substrate, a first purge step in which a purge gas is provided on the substrate to purge the first process gas which has not been absorbed on the substrate, a reaction step in which a gas containing tungsten is provided on the substrate as a second process gas to form a unit deposition film on the substrate, a second purge step in which a purge gas is provided on the substrate to purge a reaction by-product on the substrate, a processing step in which a processing gas containing a hydrogen (H) element is provided on the substrate to reduce the concentration of an impurity in the unit deposition film, and a third purge step in which a purge gas is provided on the substrate to purge the processing gas on the substrate.

A method of manufacturing a semiconductor structure includes loading the substrate from a first load lock chamber into a first processing chamber; disposing a conductive layer over the substrate in the first processing chamber; loading the substrate from the first processing chamber into the first load lock chamber; loading the substrate from the first load lock chamber into an enclosure filled with an inert gas and disposed between the first load lock chamber and a second load lock chamber; loading the substrate from the enclosure into the second load lock chamber; loading the substrate from the second load lock chamber into a second processing chamber; disposing a conductive member over the conductive layer in the second processing chamber; loading the substrate from the second processing chamber into the second load lock chamber; and loading the substrate from the second load lock chamber into a second load port.