The present disclosure provides a semiconductor device structure with a manganese-containing conductive plug and a method for forming the semiconductor device structure. The semiconductor device structure includes a first conductive layer disposed over a semiconductor substrate, and a dielectric layer disposed over the first conductive layer. The semiconductor device structure also includes a first conductive plug penetrating through the dielectric layer and in a pattern-dense region, and a lining layer covering the dielectric layer and the first conductive plug. The lining layer and the first conductive plug include manganese. The semiconductor device structure further includes a second conductive plug penetrating through the lining layer and the dielectric layer and in a pattern-loose region. The second conductive plug is separated from the dielectric layer by a portion of the lining layer. In addition, the semiconductor device structure includes a second conductive layer covering the lining layer and the second conductive plug.

A method includes, for example, providing an intermediate semiconductor structure comprising a metallic layer, a patternable layer disposed over the metallic layer, and a hard mask disposed over the patternable layer, the intermediate semiconductor structure comprising a plurality of vias extending through the hard mask onto the metallic layer, depositing a sacrificial barrier layer over the intermediate semiconductor structure and in the plurality of vias, removing a portion of the sacrificial barrier layer between the plurality of vias while maintaining a portion of the sacrificial barrier layer in the plurality of vias, forming a trench in the patternable layer between the removed portion of the sacrificial barrier layer and the plurality of vias, and removing the remaining portions of the sacrificial barrier layer from the plurality of vias.

Object is to provide an etching solution which generates less foam and can etch copper or copper alloy at high selectivity when used in a step of etching copper or 5 copper alloy in an electronic substrate having both of copper or copper alloy and nickel. The etching solution to be used in a step of selectively etching copper or copper alloy in an electronic substrate having both of copper or copper alloy and nickel has, as essential components thereof, (A) a linear alkanolamine, (B) a chelating agent having an acid group in the molecule thereof, and (C) hydrogen peroxide.

A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.

A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

According to a preferred embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device includes: a substrate having a first region and a second region; a first contact plug on the first region, and a second contact plug on the second region. Preferably, the first contact plug includes a first interfacial layer having a first conductive type and a first work function metal layer having the first conductive type on the first interfacial layer, and the second contact plug includes a second interfacial layer having a second conductive type and a second work function metal layer having the second conductive type on the second interfacial layer.

The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.

The semiconductor device may include an insulating interlayer on the substrate, the substrate including a contact region at an upper portion thereof, a main contact plug penetrating through the insulating interlayer and contacting the contact region, the main contact plug having a pillar shape and including a first barrier pattern and a first metal pattern, and an extension pattern surrounding on an upper sidewall of the main contact plug, the extension pattern including a barrier material. In the semiconductor device, an alignment margin between the contact structure and an upper wiring thereon may increase. Also, a short failure between the contact structure and the gate electrode may be reduced.

A method of forming an interconnect with a bamboo grain microstructure. The method includes forming a conductive filler layer in a trench of an insulating layer to a predetermined depth such that an aspect ratio of a top portion of the trench is reduced to a threshold level, depositing a metal layer over the conductive filler layer in the top potion of the trench, the metal layer having a plurality of small grains, and annealing the metal layer to provide a bamboo grain microstructure having larger grains than grain boundaries of the plurality of small grains.

A method of selectively locating a barrier layer on a substrate includes forming a barrier layer on a surface of the substrate. The barrier layer comprises of a metal element and a non-metal element. The barrier layer may also be formed from a metal element and non-metal element. The method further includes forming an electrically conductive film layer on the barrier layer, and forming a metallic portion in the electrically conductive film layer. The method further includes selectively ablating portions of the barrier layer from the dielectric layer to selectively locate place the barrier layer on the substrate.