A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer arranged on sidewalls, wherein the contact includes a portion that is laterally surrounded by an interlevel dielectric (ILD); depositing another layer of ILD on the contact; etching a first opening in the ILD to expose a surface of the contact; removing the liner layer of the contact to expose a portion of the cobalt core; etching the ILD that laterally surrounds the contact to form a second opening beneath the first opening, the second opening having a width that is less than the first opening; depositing a liner on sidewalls of the first opening, the second opening, and directly on the cobalt core; and depositing a metal on the liner layer to form an interconnect structure.

A semiconductor device comprising a gate electrode on a substrate, a source/drain pattern on the substrate on a side of the gate electrode, and a gate contact plug on the gate electrode are disclosed. The gate contact plug may include a first gate contact segment, and a second gate contact segment that extends in a vertical direction from a top surface of the first gate contact segment. An upper width of the first gate contact segment may be greater than a lower width of the second gate contact segment.

A semiconductor device includes a first raised feature in a NFET region on a substrate, a first n-type doped epitaxial semiconductor material grown on the first raised feature, the first n-type doped epitaxial material having a first upward facing surface and a first downward facing surface, a first contact metal on the first downward facing surface, and a second contact metal on the first upward facing surface. The device further includes a second raised feature in a PFET region on the substrate, a second p-type doped epitaxial semiconductor material grown on the second raised feature, the second p-type doped epitaxial material having a second upward facing surface and a second downward facing surface, a third contact metal on the second downward facing surface, and a fourth contact metal on the second upward facing surface, wherein the fourth contact metal is different from the second contact metal.

A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first metal layer and recessing the barrier material to form a thickness of the barrier material on the first metal layer in the via, the thickness forming an ion flow barrier. A second metal layer is deposited in the via over the ion flow barrier such that, during operation, the ion flow barrier reduces ion flow between the first metal layer and the second metal layer while maintaining low resistance.

A semiconductor device structure, along with methods of forming such, are described. The structure includes a first and second gate electrode layers, and a dielectric feature disposed between the first and second gate electrode layers. The dielectric feature has a first surface. The structure further includes a first conductive layer disposed on the first gate electrode layer. The first conductive layer has a second surface. The structure further includes a second conductive layer disposed on the second gate electrode layer. The second conductive layer has a third surface, and the first, second, and third surfaces are coplanar. The structure further includes a third conductive layer disposed over the first conductive layer, a fourth conductive layer disposed over the second conductive layer, and a dielectric layer disposed on the first surface of the dielectric feature. The dielectric layer is disposed between the third conductive layer and the fourth conductive layer.

A multi-layer device comprising a barrier or adhesion layer located on a portion of a first top surface of a first layer, a conductive metal layer located on barrier or adhesion layer; and a dielectric layer located on top of the first layer, wherein the dielectric layer is in direct contact with the sidewall of the conductive metal layer.

A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, and a gate structure disposed on the fin structure adjacent to the S/D region. The gate structure includes a gate stack disposed on the fin structure and a gate capping structure disposed on the gate stack. The gate capping structure includes a conductive gate cap disposed on the gate stack and an insulating gate cap disposed on the conductive gate cap. The semiconductor device further includes a first contact structure disposed over the gate stack. A portion of the first contact structure is disposed within the gate capping structure and is separated from the gate stack by a portion of the conductive gate cap.

A method for forming a FinFET device structure is provided. The method includes forming a gate dielectric layer over a fin structure. The method also includes forming a gate electrode layer over the gate dielectric layer. The method further includes forming a first dielectric layer formed over the gate dielectric layer. In addition, the method includes forming a first conductive layer on the gate dielectric layer. A bottom surface of the first conductive layer is in direct contact a top surface of the gate electrode layer, a sidewall of the first conductive layer is in direct contact the first dielectric layer and spaced apart from the gate dielectric layer.

The present invention provides a barrier layer removal method, wherein the barrier layer includes at least one layer of ruthenium or cobalt, the method comprising: removing the barrier layer including ruthenium or cobalt formed on non-recessed areas of a semiconductor structure by thermal flow etching. The present invention further provides a semiconductor structure forming method, comprising: providing a semiconductor structure which includes a dielectric layer, a hard mask layer formed on the dielectric layer, recessed areas formed on the hard mask layer and the dielectric layer, a barrier layer including at least one layer of ruthenium or cobalt formed on the hard mask layer, sidewalls of the recessed areas and bottoms of the recessed areas, a metal layer formed on the barrier layer and filling the recessed areas; removing the metal layer formed on the non-recessed areas and the metal in the recessed areas, and remaining a certain amount of metal in the recessed areas; removing the barrier layer including ruthenium or cobalt formed on the non-recessed areas, and the hard mask layer by thermal flow etching.

Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect structures include one or more electronic devices formed on a substrate. A first interlevel dielectric (ILD) layer is over the one or more electronic devices. The interconnect structure includes a first trench in the first ILD layer. A tungsten contact fills the first trench and is in electrical contact with the one or more electronic devices. A second ILD layer is over the first ILD layer. The interconnect structure includes a second trench in the second ILD layer. Diffusion barrier liners bound all sides of the second trench except at a surface of the tungsten contact. The interconnect structure includes a copper wire filling the second trench, the copper wire in direct contact with the tungsten contact and with the diffusion barrier liners.