A method for producing a thin-film solar module with serially connected solar cells and related device. A back electrode layer is deposited on one side of a flat substrate and subdivided by first patterning trenches. An absorber layer is deposited over the back electrode layer and subdivided by second patterning trenches. A front electrode layer is deposited over the absorber layer. At least the front electrode layer is subdivided by third patterning trenches. A direct succession of a first patterning trench, a second patterning trench, and two adjacent third patterning trenches forms a patterning zone. The third patterning trenches are produced by laser ablation through a pulsed laser beam, where one third patterning trench is produced with laser pulses of higher energy and the other third patterning trench of the patterning zone is produced with laser pulses of lower energy.

An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.

The present invention provides a manufacturing method of an array substrate, including steps of: providing a flexible substrate layer, forming a buffer layer, forming an active layer, forming a gate insulating layer, forming a gate layer, forming an interlayer insulating layer, forming a source and drain layer, forming an organic planarization layer, forming an anode layer. An array substrate manufactured by the above manufacturing method, and the array substrate includes laminated a flexible substrate layer, a buffer layer, an active layer, a gate insulating layer, a gate layer, an interlayer insulating layer, a source and drain layer, an organic planarization layer, and an anode layer, which are disposed in a stack.

A substrate having a first surface with at least one division line and an opposite second surface is processed by attaching a protective sheeting to the first surface and applying a laser beam to the protective sheeting to form a plurality of alignment marks in the protective sheeting. The substrate has a backside layer on the second surface. A laser beam is applied to the substrate from the side of the first surface. The substrate is transparent to the laser beam and the focal point of the laser beam is located inside the substrate which is closer to the second surface than to the first surface, to form a plurality of alignment marks in the backside layer. Substrate material is removed along the division line from the side of the second surface. The alignment marks are used for aligning the substrate material removing means relative to the division line.

An electronic component includes a first insulating layer, a resistance layer including a metal thin film that is formed on the first insulating layer, the resistance layer having a first end portion, a second end portion and a central portion between the first end portion and the second end portion, a first electrode having a first contact portion and a second contact portion spaced away from the first contact portion both of which are in contact with the resistance layer at a portion of the first end portion side with respect to the central portion of the resistance layer, a notched portion formed in the first end portion of the resistance layer and between the first contact portion and the second contact portion, and a second electrode having a contact portion in contact with the resistance layer at a portion of the second end portion side with respect to the central portion of the resistance layer.

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form modified layers in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet.

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of blowing air to each device chip from the polyester sheet side to push up each device chip through the polyester sheet and picking up each device chip from the polyester sheet.

A wafer processing method includes a polyester sheet providing step of positioning a wafer in an inside opening of a ring frame and providing a polyester sheet on a back side or a front side of the wafer and on a back side of the ring frame, a uniting step of heating the polyester sheet as applying a pressure to the polyester sheet to thereby unite the wafer and the ring frame through the polyester sheet by thermocompression bonding, a dividing step of applying a laser beam to the wafer to form shield tunnels in the wafer, thereby dividing the wafer into individual device chips, and a pickup step of cooling the polyester sheet, pushing up each device chip through the polyester sheet, and picking up each device chip from the polyester sheet.

There is provided a manufacturing method of a wafer. The manufacturing method of a wafer includes a preparation step of preparing a wafer that includes a substrate and a stacked body disposed on the front surface side of the substrate and that has a device region and an outer circumferential surplus region, the device region having a plurality of devices disposed in a plurality of regions marked out by a plurality of planned dividing lines arranged to intersect each other, the outer circumferential surplus region surrounding the device region, and a laser processed groove forming step of forming laser processed grooves along the planned dividing lines through executing irradiation with a first laser beam with a wavelength having absorbability with respect to the stacked body, along the planned dividing lines from the side of the stacked body of the wafer.

A semiconductor structure, a memory device, a semiconductor device and a semiconductor device manufacturing method are provided. The semiconductor structure includes a die, a power bus and a first pad assembly. The power bus is disposed on the die and extends in a predetermined direction. The first pad assembly is arranged on one side of the power bus. The first pad assembly includes at least four pads separated from one another along the predetermined direction by the first, the second and the third gaps. The first gap and the second gap both have a width larger than a width of the third gap and the first pad assembly includes a power pad coupled to the power bus and located between the first gap and the second gap. The power pad and the first and second gaps are all located between opposing ends of the power bus.