A semiconductor device includes a semiconductor part, first and second electrodes, and a control electrode. The semiconductor part is provided between the first and second electrodes. The control electrode is provided in a trench of the semiconductor part between the semiconductor part and the second electrode. The semiconductor part includes first to third layers. The first layer of a first conductivity type extends between the first and second electrodes. The second layer of a second conductivity type is provided between the first layer and the second electrode. The second layer is connected to the second electrode. The third layer of the second conductivity type is provided between the second layer and the control electrode. The third layer includes a second-conductivity-type impurity with a higher concentration than a second-conductivity-type impurity of the second layer. The third layer contacts the second electrode, and is electrically connected to the second electrode.

A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 MΩ.

A semiconductor device includes a semiconductor body having a base region incorporating a field stop zone where the base region and the field stop zone are both formed using an epitaxial process. Furthermore, the epitaxial layer field stop zone is formed with an enhanced doping profile to realize improved soft-switching performance for the semiconductor device. In some embodiments, the enhanced doping profile formed in the field stop zone includes varying, non-constant doping levels. In some embodiments, the enhanced doping profile includes one of an extended graded doping profile, a multiple stepped flat doping profile, or a multiple spike doping profile. The epitaxial layer field stop zone of the present invention enables complex field stop zone doping profiles to be used to obtain the desired soft-switching characteristics in the semiconductor device.

A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.

Provided is a semiconductor device including a buffer region. Provided is a semiconductor device including: semiconductor substrate of a first conductivity type; a drift layer of the first conductivity type provided in the semiconductor substrate; and a buffer region of the first conductivity type provided in the drift layer, the buffer region having a plurality of peaks of a doping concentration, wherein the buffer region has: a first peak which has a predetermined doping concentration, and is provided the closest to a back surface of the semiconductor substrate among the plurality of peaks; and a high-concentration peak which has a higher doping concentration than the first peak, and is provided closer to an upper surface of the semiconductor substrate than the first peak is.

A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.

A vertical IGBT device is provided. The vertical IGBT device includes a substrate having a first conductivity type. A drift region of the first conductivity type formed on the top surface of the substrate. The bottom surface of the substrate is patterned to have an array of mesas and grooves. The mesas and the grooves are formed in an alternating fashion so that each mesa is separated from the other by a groove including a groove surface. In the groove surface, a top buffer region of the first conductivity type and a bottom buried region of a second conductivity type are formed extending laterally between the mesas adjacent each groove surface. Each mesa includes an upper region of the first conductivity and a lower region of the second conductivity.

In a surface layer of a rear surface of the semiconductor substrate, an n.sup.+-type cathode region and a p-type cathode region are each selectively provided. The n.sup.+-type cathode region and the p-type cathode region constitute a cathode layer and are adjacent to each other along a direction parallel to the rear surface of the semiconductor substrate. The n.sup.+-type cathode region and the p-type cathode region are in contact with a cathode electrode. In an n.sup.-type drift layer, plural n-type FS layers are provided at differing depths deeper from the rear surface of the semiconductor substrate than is the cathode layer. With such configuration, in a diode, a tradeoff relationship of forward voltage reduction and reverse recovery loss reduction may be improved and soft recovery may be realized.

Performance of a semiconductor device is improved. An active cell region has a first gate electrode that extends in a Y direction and receives a gate potential, and a second gate electrode that extends in the Y direction and receives an emitter potential. A hybrid cell region including a p-type base region and an n-type emitter region is disposed in the active cell region. An n-type isolation region adjacent to the hybrid cell region in the Y direction is formed in the active cell region excluding the hybrid cell region. Hence, even if the p-type base region or a p-type floating region is formed in the active cell region excluding the hybrid cell region, such a p-type region is isolated from the base region in the hybrid cell region by the isolation region.

An RC IGBT with an n-barrier region in a transition section between a diode section and an IGBT section is presented.