On a front surface side of an n.sup. semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n.sup.+ emitter region are the IGBT emitter region and the p base layers not having the n.sup.+ emitter region are the FWD anode region. A lateral width of an n.sup.+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n.sup.+ cathode region is 50 m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.

A semiconductor device, which is a diode, includes the following: an n cathode layer, which is an n-type region, disposed in a surface layer of a semiconductor substrate; a p cathode layer, which is a p-type region, disposed in the surface layer; and a cathode electrode, which is a metal electrode, in contact with both of the n cathode layer and the p cathode layer. The cathode electrode includes a first metal layer in contact with both of the n cathode layer and the p cathode layer, and a second metal layer disposed on the first metal layer. A contact surface between the first metal layer and the second metal layer has an oxygen concentration lower than the oxygen concentration of a contact surface between the first metal layer, and the n cathode layer and the p cathode layer.

A semiconductor device may include a semiconductor substrate, an upper electrode and a lower electrode. The semiconductor substrate may include: a p-type anode region being in contact with the upper electrode; an n-type cathode region being in contact with the lower electrode; an n-type drift region interposed between the anode region and the cathode region. The semiconductor substrate may further include a barrier region interposed between the anode region and the drift region; and an n-type pillar region extending between the barrier region and the upper electrode. The barrier region may include a multi-layer structure in which a p-type second barrier layer is interposed between an n-type first barrier layer and an n-type third barrier layer. The first barrier layer may be in contact with the anode region and is connected to the upper electrode via the pillar region.

A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.

A semiconductor device has a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a first conductive layer disposed on a main surface of the first semiconductor region, and a second conductive layer disposed on a main surface of the second semiconductor region. The first conductive layer has a first diffusion layer of the first conductivity type, a plurality of second diffusion layers of the first conductivity type, the second diffusion layers having higher impurity concentration than the first diffusion layer, and a plurality of third diffusion layers of the first conductivity type that are included in the first semiconductor region, or are arranged apart from one another to contact the first and second semiconductor regions, the third diffusion layers being arranged apart from the plurality of second diffusion layers and having higher impurity concentration than the first diffusion layer.

Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.

A semiconductor device is provided, the semiconductor device including: a semiconductor substrate having a first-conductivity-type drift region; one or more transistor portions provided in the semiconductor substrate; and one or more diode portions provided in the semiconductor substrate, wherein both the transistor portions and the diode portions have trench portions that lie from a top surface of the semiconductor substrate to the drift region and include conductive portions, and in a top view of the semiconductor substrate, a main direction of the trench portions in the transistor portions is different from a main direction of the trench portions in the diode portions.

A semiconductor device includes a first semiconductor layer, a second semiconductor layer selectively provided on the first semiconductor layer, a third semiconductor layer selectively provided on the second semiconductor layer, and a control electrode facing a portion of the second semiconductor layer via a first insulating film. The device further includes a fourth semiconductor layer provided on a lower surface side of the first semiconductor layer, a fifth semiconductor layer arranged with the fourth semiconductor layer along a lower surface of the first semiconductor layer, and a sixth semiconductor layer provided between the first and fifth semiconductor layers. The sixth semiconductor layer is connected to the fourth semiconductor layer. The device includes a connecting portion positioned between the first and fifth semiconductor layers. The connecting portion electrically connects the fifth semiconductor layer to the first semiconductor layer, and the sixth semiconductor layer is not provided at the connecting portion.

A semiconductor device may include a semiconductor substrate. A semiconductor substrate may include a diode region and an IGBT region provided adjacent to the diode region. The IGBT region may include a plurality of first conductive-type low concentration regions provided between a buffer region and a collector region, arranged with intervals therebetween in a direction parallel to the semiconductor substrate, and having a lower impurity concentration than the collector region. The collector region may include a first contact portion that is in contact with the buffer region between the low concentration regions adjacent to each other.

A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.