An electronic device includes a first semiconductor die with a first FET having a drain connected to a switching node, a source connected to a reference node, and a gate connected to a first switch control node. The first die also includes a diode-connected bipolar transistor that forms a temperature diode next to the first FET. The temperature diode includes a cathode connected to the reference node, and an anode connected to a bias node. The electronic device also includes a second semiconductor die with a second FET, and a package structure that encloses the first and second semiconductor dies.

A semiconductor device includes a first semiconductor layer, a second semiconductor layer selectively provided on the first semiconductor layer, a third semiconductor layer selectively provided on the second semiconductor layer, and a control electrode facing a portion of the second semiconductor layer via a first insulating film. The device further includes a fourth semiconductor layer provided on a lower surface side of the first semiconductor layer, a fifth semiconductor layer arranged with the fourth semiconductor layer along a lower surface of the first semiconductor layer, and a sixth semiconductor layer provided between the first and fifth semiconductor layers. The sixth semiconductor layer is connected to the fourth semiconductor layer. The device includes a connecting portion positioned between the first and fifth semiconductor layers. The connecting portion electrically connects the fifth semiconductor layer to the first semiconductor layer, and the sixth semiconductor layer is not provided at the connecting portion.

A semiconductor device is provided, including: a semiconductor substrate; a transistor section provided in the semiconductor substrate; and a diode section provided in the semiconductor substrate being adjacent to the transistor section, wherein the diode section includes: a second conductivity-type anode region; a first conductivity-type drift region; a first conductivity-type cathode region; a plurality of dummy trench portions arrayed along a predetermined array direction; a contact portion provided along an extending direction of the plurality of dummy trench portions that is different from the array direction; and a lower-surface side semiconductor region provided directly below a portion of the contact portion at an outer end in the extending direction.

A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

To provide a semiconductor device that has barrier metal and has a small variation in a threshold voltage. A semiconductor device is provided, including a semiconductor substrate, an interlayer dielectric film arranged on an upper surface of the semiconductor substrate, a titanium layer provided on the interlayer dielectric film, and a titanium nitride layer provided on the titanium layer, where the interlayer dielectric film is provided with an opening that exposes a part of the upper surface of the semiconductor substrate, the titanium layer and the titanium nitride layer are also provided within the opening, and the titanium layer arranged in contact with the semiconductor substrate and on a bottom portion of the opening is entirely titanium-silicided.

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

A semiconductor device includes pads arrayed between a region where a transistor portion or a diode portion is disposed and a first end side on an upper surface of a semiconductor substrate, and a gate runner portion that transfers a gate voltage to the transistor portion. The gate runner portion has a first gate runner disposed passing between the first end side of the semiconductor substrate and at least one of the pads in the top view, and a second gate runner disposed passing between at least one of the pads and the transistor portion in the top view. The transistor portion is also disposed in the inter-pad regions, the gate trench portion disposed in the inter-pad regions is connected to the first gate runner, and the gate trench portion arranged so as to face the second gate runner is connected to the second gate runner.

A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.

A method for manufacturing a semiconductor device having an SiC-IGBT and an SiC-MOSFET in a single semiconductor chip, including forming a second conductive-type SiC base layer on a substrate, and selectively implanting first and second conductive-type impurities into surfaces of the substrate and base layer to form a collector region, a channel region in a surficial portion of the SiC base layer, and an emitter region in a surficial portion of the channel region, the emitter region serving also as a source region of the SiC-MOSFET.

A semiconductor device including: drift regions formed on a semiconductor substrate; gate trench portions extending in predetermined extending directions from a semiconductor substrate upper surface; first and second mesa portions being in direct contact with one and the other sides of a gate trench portion side wall respectively; accumulation regions being in direct contact with the gate trench portions, above the drift regions, and having doping concentration higher than drift region concentration; a base region being in direct contact with the gate trench portions, above the accumulation regions; emitter regions being in direct contact with the one side wall of a gate trench portion on a semiconductor substrate upper surface in the first mesa portion, and having doping concentration higher than drift region concentration; and electrically floating second conductivity type floating regions provided spaced from the gate trench portion below the base region in the second mesa portion is provided.