An integrated circuit includes; a substrate including a single active region, a first active resistor formed on the substrate, and a transistor including a first junction area in the single active region. The first active resistor and the transistor are electrically connected through the first junction area. The first active resistor is formed between a first node and a second node included in the first junction area. The first node is connected to a first contact, and the second node is connected to a second contact.

The disclosure relates to power semiconductor devices in GaN technology. The disclosure proposes an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. In other embodiments a pull-down network for the switching-off of the high threshold voltage GaN transistor is formed by additional auxiliary low-voltage GaN transistors and resistive elements connected in parallel or in series with the low-voltage auxiliary GaN transistor.

The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N.sup.+-type diffusion region, an N-type diffusion region, a P.sup.+-type diffusion region, a P-type diffusion region, an N.sup.+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N.sup.+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N.sup.+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N.sup.+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N.sup.+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.

A transistor device includes a substrate, a source region provided on the substrate, a drain region spaced apart from the source region in a direction parallel to a top surface of the substrate, a pair of constant current generating patterns provided in the substrate to be adjacent to the source region and the drain region, respectively, a gate electrode provided on the substrate and between the source region and the drain region, and a gate insulating film interposed between the gate electrode and the substrate, wherein, the pair of constant current generating patterns generate a constant current between the drain region and the substrate, and the constant current is independent from a gate voltage applied to the gate electrode.

Embodiments herein describe techniques, systems, and method for a semiconductor device that may include an III-V transistor with a resistive gate contact. A semiconductor device may include a substrate, and a channel base including a layer of GaN above the substrate. A channel stack may be above the channel base, and may include a layer of GaN in the channel stack, and a polarization layer above the layer of GaN in the channel stack. A gate stack may be above the channel stack, where the gate stack may include a gate dielectric layer above the channel stack, and a resistive gate contact above the gate dielectric layer. The resistive gate contact may include silicon (Si) or germanium (Ge). Other embodiments may be described and/or claimed.

Power semiconductor devices in GaN technology include an integrated auxiliary (double) gate terminal and a pulldown network to achieve a normally-off (E-Mode) GaN transistor with threshold voltage higher than 2V, low gate leakage current and enhanced switching performance. The high threshold voltage GaN transistor has a high-voltage active GaN device and a low-voltage auxiliary GaN device wherein the high-voltage GaN device has the gate connected to the source of the integrated auxiliary low-voltage GaN transistor and the drain being the external high-voltage drain terminal and the source being the external source terminal, while the low-voltage auxiliary GaN transistor has the gate (first auxiliary electrode) connected to the drain (second auxiliary electrode) functioning as an external gate terminal. A pull-down network for the switching-off of the high threshold voltage GaN transistor may be formed by additional auxiliary low-voltage GaN transistors and resistive elements connected with the low-voltage auxiliary GaN transistor.

The present disclosure provides an integrated circuit (IC) structure that includes a fin active region on a substrate; a metal gate stack on the fin active region; a source and a drain on the fin active region, wherein the metal gate stack spans from the source to the drain; an interlayer dielectric (ILD) layer disposed on the source and the drain; a first conductive feature and a second conductive feature formed in the ILD layer and being aligned on the source and the drain, respectively; and a dielectric material layer surrounding the first and second conductive features. The dielectric material layer continuously extends to a bottom surface of the first conductive feature and isolates the first conductive feature from the source and the second conductive feature contacts the drain.

Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

A semiconductor device includes a semiconductor substrate and a resistance element provided above the semiconductor substrate, the resistance element includes a conductive pattern using a gate electrode film formed simultaneously with a gate electrode film arranged on a side surface of a semiconductor nanowire of a VNW transistor, and there is fabricated the semiconductor device that includes the VNW transistor having the semiconductor nanowire and the resistance element having sufficient electrical resistance.