A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

On a front surface side of an n.sup. semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n.sup.+ emitter region are the IGBT emitter region and the p base layers not having the n.sup.+ emitter region are the FWD anode region. A lateral width of an n.sup.+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n.sup.+ cathode region is 50 m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.

A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

A semiconductor device includes a heterojunction bipolar transistor and a bump. The heterojunction bipolar transistor (HBT) includes a plurality of unit transistors. The bump is electrically connected to emitters of the plurality of unit transistors through respective overlying conductor filled via openings that overlap in a plan view with a width portion of the bump. The semiconductor device reduces heat resistance in an HBT cell by satisfying two conditions, the first of which is related to specific sizing and positioning of a width portion of the overlying via opening relative to the width portion of the bump, and the second of which is related to positioning the base electrode entirely within a specific region of the width portion of the overlapping overlying via opening.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.

A semiconductor device is provided, in which a loss of a sensing element is small. A semiconductor device including a semiconductor substrate is provided, the semiconductor device including: an upper-surface electrode that is provided on an upper surface of the semiconductor substrate; a sensing electrode that is provided on the upper surface of the semiconductor substrate and is separated from the upper-surface electrode; a lower-surface electrode that is provided on a lower surface of the semiconductor substrate; a main transistor portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; a main diode portion that is provided on the semiconductor substrate and is connected to the upper-surface electrode and the lower-surface electrode; and a sense diode portion that is provided to the semiconductor substrate and is connected to the sensing electrode and the lower-surface electrode.

A system and method for fabricating metal insulator metal capacitors while managing semiconductor processing yield and increasing capacitance per area are described. A semiconductor device fabrication process places an oxide layer on top of a metal layer. A photoresist layer is formed on top of the oxide layer and etched with repeating spacing. One of a variety of lithography techniques is used to alter the distance between the spacings. The process etches trenches into areas of the oxide layer unprotected by the photoresist layer and strips the photoresist layer. The top and bottom corners of the trenches are rounded. The process deposits a bottom metal, a dielectric, and a top metal on the oxide layer both on areas with the trenches and on areas without the trenches. The process completes the metal insulator metal capacitor with metal nodes contacting each of the top plate and the bottom plate.

On a front surface side of an n.sup. semiconductor substrate, an emitter electrode and trench gates each including a p base layer, a trench, a gate oxide film and a gate electrode are provided in an IGBT region and a FWD region. Among p base layers each between adjacent trenches, p base layers having an n.sup.+ emitter region are the IGBT emitter region and the p base layers not having the n.sup.+ emitter region are the FWD anode region. A lateral width of an n.sup.+ cathode region is narrower than a lateral width of the FWD anode region. A difference of a lateral width of the FWD anode region and a lateral width of the n.sup.+ cathode region is 50 m or more. Thus, a semiconductor device may be provided that reduces the forward voltage drop while suppressing waveform oscillation during reverse recovery and having soft recover characteristics.