An image sensor includes a photodiode disposed in a semiconductor substrate having a first surface and a second surface opposite to the first surface. A floating diffusion is disposed in the semiconductor substrate. A transfer transistor is configured for coupling the photodiode to the floating diffusion. The transfer transistor includes a vertical transfer gate extending a first depth in a depthwise direction from the first surface into the semiconductor substrate. A transistor is coupled to the floating diffusion. The transistor includes: a planar gate disposed proximate to the first surface of the semiconductor substrate; and a plurality of vertical gate electrodes, each extending a respective depth into the semiconductor substrate from the planar gate in the depthwise direction. The respective depth of at least one of the plurality of vertical gate electrodes is the same as the first depth of the vertical transfer gate.

Provided are a solid-state imaging element, which suppresses occurrence of a dark current and a white spot and even suppresses occurrence of a residual image, and a manufacturing method for the solid-state imaging element. A solid-state imaging element (1) is provided with: a gate electrode (4) above a substrate (2); a charge storage region (5) formed at a position inside the substrate (2) and apart from a top surface (2a) of the substrate (2); a read region (6) formed at a position inside the substrate (2) and on the opposite side to the charge storage region (5) with the gate electrode (4) interposed therebetween; a channel region (7, 8) formed inside the substrate (2) and immediately below the gate electrode (4); and a shield region (9) and an intermediate region (10) formed inside the substrate (2) and between the top surface (2a) of the substrate (2) and the charge storage region (5). The intermediate region (10) is formed at a position inside the substrate (2) and between the channel region (7, 8) and the shield region (9), and is in contact with each of the channel region (7, 8) and the shield region (9), and a concentration of first conductive type impurities in the intermediate region (10) is lower than a concentration of the first conductive type impurities in the shield region (9).

An image sensor element includes a transfer transistor TX, a LOFIC select transistor LF, a photodiode PD, and a first overflow path OFP. The transfer transistor TX outputs a readout signal from a first end. The LOFIC select transistor LF includes a first end connected to a second end of the transfer transistor TX, and a second end connected to a capacitor. The photodiode PD is connected in common to a third end of the transfer transistor and a third end of the LOFIC select transistor LF. The first overflow path OFP is formed between the photodiode PD and a second end of the LOFIC select transistor LF. Each of the transfer transistor TX and the LOFIC select transistor LF is configured with a vertical gate transistor.

A pixel cell, a method for manufacturing the same and an image sensor including the same are provided. The pixel cell includes: a substrate; a photodiode, a pass transistor and a floating diffusion structure respectively formed on the substrate, in which the pass transistor is formed between the photodiode and the floating diffusion structure; and a PINNED structure, formed on the substrate and connected with the floating diffusion structure, in which a reset voltage of the floating diffusion structure is higher than a depletion voltage of the PINNED structure.

An exemplary embodiment of the present invention provides an infrared image sensor including: a sensor pixel connected with a data lead-out line and a scan line disposed on a surface of a substrate; a wavelength converter positioned in the sensor pixel and disposed in an internal movement path of infrared rays, including an anti-Stokes material that absorbs infrared rays and converts them into visible rays to emit them; and a photosensor part positioned in the sensor pixel to sense the visible rays converted by the wavelength converter.

In an active pixel image sensor using CMOS technology formed within a substrate of a first type of conductivity P, each pixel comprises a photosensitive element PHD producing charges under the effect of light and a structure for multiplication of charges EM. The multiplication structure comprises at least one isolated multiplication gate G1, G2 adjacent to a pinned diode DI at a fixed internal potential V.sub.bi, and the isolated gate is adapted for receiving a series of alternations of potentials, alternately creating under the isolated gate a charge collection well and a barrier, relative to the internal potential level of the diode DI. The isolated gate and the semiconductor region under the isolated gate are configured in such a manner that the charge collection well created under the gate comprises two parts: a first part a, adjacent to the pinned diode, at a potential level further from the photodiode internal potential level than that of a second part b, this second part being adjacent or not to the pinned diode.

An imaging device that facilitates pooling processing. A pixel region includes a plurality of pooling modules and an output circuit, the pooling module includes a pooling circuit and a comparison module, the pooling circuit includes a plurality of pixels and an arithmetic circuit, and the comparison module includes a plurality of comparison circuits and a determination circuit. The pixel can obtain a first signal through photoelectric conversion, and can multiply the first signal by a given scaling factor to generate a second signal. The pooling circuit adds a plurality of second signals in the arithmetic circuit to generate a third signal, the comparison module compares a plurality of third signals and outputs the largest third signal to the determination circuit, and the determination circuit determines the largest third signal and binarizes it to generate a fourth signal. In the imaging device, the pooling module performs pooling processing in accordance with the number of pixels and outputs data obtained by the pooling processing.

An image sensor includes a first lower chip, and an upper chip on and bonded to the first lower chip. The first lower chip and the upper chip collectively provide a plurality of pixels. A respective pixel of the plurality of pixels includes a photoelectric conversion element, a floating diffusion region, a ground region, and a transfer gate in the upper chip, and a plurality of lower transistors in the first lower chip. A first lower transistor among the plurality of lower transistors includes a plurality of first channel layers stacked vertically, and a first gate on the plurality of first channel layers.

Provided is a solid state image pickup element including a MOS type transistor which amplifies a signal which is based on electric charges generated in a photoelectric conversion unit of a pixel. A channel region of the transistor is divided into a source-side region and a drain-side region. When a conductivity type of the transistor is defined as a first conductivity type and a conductivity type which is opposite to the first conductivity type is defined as a second conductivity type, a concentration of a first conductivity type impurity in the source-side region is higher than a concentration of the first conductivity type impurity in the drain-side region or a concentration of a second conductivity type impurity in the drain-side region is higher than a concentration of the second conductivity type impurity in the source-side region.

An image sensor includes a first semiconductor substrate, a photoelectric conversion region in the first semiconductor substrate, and a buried insulating film on the first semiconductor substrate. The buried insulating film covers a first region of the first semiconductor substrate and exposes a second region of the first semiconductor substrate. The sensor includes a second semiconductor substrate on the buried insulating film, an operating gate structure defining a first channel of a first conductive type in the second semiconductor substrate, and a transfer gate structure defining a second channel of a second conductive type different from the first conductive type in the second region of the first semiconductor substrate.