The present disclosure is directed to a diode with a semiconductor body of silicon including a cathode region, which has a first conductivity type and is delimited by a front surface; and an anode region, which has a second conductivity type and extends into the cathode region from the front surface. The diode further includes a barrier region of cobalt disilicide, arranged on the anode region; and a metallization region of aluminum or of an aluminum alloy, arranged on the barrier region. The barrier region contacts the anode region.

Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

A metal oxide semiconductor field effect transistor preferably fabricated with a silicon-on-insulator process has a first semiconductor region and a second semiconductor region in a spaced relationship thereto A body structure is defined by a channel segment between the first semiconductor region and the second semiconductor region, and a first extension segment structurally contiguous with the channel segment. A shallow trench isolation structure surrounds the first semiconductor region, the second semiconductor region, and the body structure, with a first extension interface being defined between the shallow trench isolation structure and the first extension segment of the body structure to reduce leakage current flowing from the second semiconductor region to the first semiconductor region through a parasitic path of the body structure.

There is provided a semiconductor device comprising: a semiconductor substrate including a drift region of a first conductivity type; an emitter region of the first conductivity type provided above the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a base region of a second conductivity type provided between the emitter region and the drift region inside the semiconductor substrate; a first accumulation region of the first conductivity type provided between the base region and the drift region inside the semiconductor substrate and having a doping concentration higher than the drift region; a plurality of trench portions provided to pass through the emitter region, the base region and first accumulation region from an upper surface of the semiconductor substrate, and provided with a conductive portion inside; and a capacitance addition portion provided below the first accumulation region to add a gate-collector capacitance thereto.

A semiconductor device includes a semiconductor substrate, a transistor section, a diode section, and a boundary section provided between the transistor section and the diode section in the semiconductor substrate. The transistor section has gate trench portions which are provided from an upper surface of the semiconductor substrate to a position deeper than that of an emitter region, and to each of which a gate potential is applied. An upper-surface-side lifetime reduction region is provided on the upper surface side of the semiconductor substrate in the diode section and a partial region of the boundary section, and is not provided in a region that is overlapped with the gate trench portion in the transistor section in a surface parallel to the upper surface of the semiconductor substrate.

A semiconductor device according to the present disclosure includes: a gate electrode provided in a gate trench and provided so as to oppose a source region via a gate insulating film; a first bottom protection region of a second conductivity type provided below the gate insulating film; a plurality of first connection regions of the second conductivity type provided at a first interval in an extension direction of the gate trench and electrically connecting the first bottom protection region and a body region; a Schottky electrode provided in a Schottky trench; a second bottom protection region of the second conductivity type provided below the Schottky electrode; and a plurality of second connection regions of the second conductivity type provided at a second interval smaller than the first interval in an extension direction of the Schottky trench and electrically connecting the second bottom protection region and the body region.

A silicon carbide layer has an active region and an outer peripheral region arranged along an outer periphery of the active region in an in-plane direction. First well regions are arranged in the active region. A second well region is arranged in the outer peripheral region. Ohmic electrodes are arranged on a second surface of the silicon carbide layer, are connected to a source electrode, are electrically and ohmically connected to the first well regions, and have surface regions ohmically contacting a part forming the second surface of the silicon carbide layer and having a second conductivity type. The active region includes a standard region part and a thinned region part between the standard region part and the outer peripheral region. The surface regions are arranged at surface density lower in the thinned region part than in the standard region part in a plan view.

Power semiconductor device capable of controlling slope of current and voltage during dynamic switching disclosed. The power semiconductor device may include a semiconductor substrate and a cell array being consisted of a plurality of transistor cells on an active area, wherein each of the plurality of transistor cells may include an emitter region, a body region, a contact region and a gate region, wherein non-uniform threshold voltages may be respectively set in the plurality of transistor cells constituting the cell array, wherein a gate signal may be applied to each of the plurality of transistor cells through an input/output unit, wherein the input/output unit may include a first gate signal path configured for supplying a gate charging current to the gate regions in each of the plurality of transistor cells and a second gate signal path configured for discharging a gate discharging current from the gate region.

A method of manufacturing a metal silicide layer comprises performing laser thermal annealing of a surface region of a silicon carbide (SiC) substrate, exposing a surface of a thus obtained silicon layer, depositing a metal layer above the exposed silicon layer, and/or thermally treating a stack of layers, comprising the silicon layer and the metal layer, to form a metal silicide layer. Alternatively and/or additionally, the method may comprise depositing a silicon layer above a SiC substrate, depositing a metal layer, and/or performing laser thermal annealing of the SiC substrate and a stack of layers above the SiC substrate to form a metal silicide layer, wherein the stack of layers comprises the silicon layer and the metal layer. Moreover, a semiconductor device is described, comprising a SiC substrate, a metal silicide layer, and a polycrystalline layer in direct contact with the SiC substrate and the metal silicide layer.

A semiconductor device includes: a semiconductor layer; a gate trench formed in the semiconductor layer; an insulating layer formed on the semiconductor layer; a gate electrode buried in the gate trench via the insulating layer; a gate wiring formed on the insulating layer and electrically connected to the gate electrode; and a protection trench formed in the semiconductor layer, wherein the semiconductor layer includes an outer peripheral region including outer edges of the semiconductor layer in a plan view and an inner region surrounded by the outer peripheral region, wherein the gate trench includes an outer peripheral gate trench portion arranged in the outer peripheral region and surrounded by the protection trench in a plan view, and wherein the outer peripheral gate trench portion and the protection trench are formed in a closed annular shape along the outer edges of the semiconductor layer in the outer peripheral region.