In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

Disclosed is a transistor including a substrate, first and second type wells in contact with each other on the substrate; and a breakdown voltage improving region including vertical high concentration doped regions according to first and second types vertically in contact from upper surfaces of the first and second type wells to an upper surface of the substrate in a portion where the first and second type wells are in contact with each other.

An electric assembly includes a semiconductor switching device with a maximum breakdown voltage rating across two load terminals in an off-state. A clamping diode is electrically connected to the two load terminals and parallel to the switching device. A semiconductor body of the clamping diode is made of silicon carbide. An avalanche voltage of the clamping diode is lower than the maximum breakdown voltage rating of the switching device.

Methods and structure are provided for programming an array of bit cells to create a unique identification code for a semiconductor structure. Random failure of a gate dielectric at a transistor is utilized to generate a binary identification code. A portion of the gate is located above a source and a portion is located above a drain, a first logic state can be applied where the gate dielectric fails source-side and a second logic state can be applied where the gate dielectric fails drain-side. The gate dielectric preferentially fails as a function of its thinness versus the thickness of a second gate dielectric of a second transistor which acts as a control for failure of the gate dielectric. Failure is initiated based upon a voltage applied to both the thin gate dielectric and the thick dielectric. A bit cell can include two or three transistors, e.g., field effect transistors.

In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A metal-oxide-semiconductor field-effect transistor (MOSFET) power device includes an active region formed on a bulk semiconductor substrate, the active region having a first conductivity type formed on at least a portion of the bulk semiconductor substrate. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.

A power transistor assembly and method of mitigating short channel effects in a power transistor assembly are provided. The power transistor assembly includes a first layer of semiconductor material formed of a first conductivity type material and a hard mask layer covering at least a portion of the first layer and having a window therethrough exposing a surface of the first layer. The power transistor assembly also includes a first region formed in the first layer of semiconductor material of a second conductivity type material and aligned with the window, one or more source regions formed of first conductivity type material within the first region and separated by a portion of the first region, and an extension of the first region extending laterally through the surface of the first layer.

In some embodiments, an apparatus comprises a semiconductor layer doped with a first-type dopant, a first region doped with the first-type dopant, a second region doped with the first-type dopant, and a third region doped with a second-type dopant, where the second-type dopant is opposite the first-type dopant. The first, second, and third regions are non-overlapping and are formed in the semiconductor layer. The third region is positioned between the first region and the second region. The apparatus also comprises a plurality of Zener implant regions buried in the semiconductor layer and the third region, where each of the plurality of Zener implant regions is configured to generate a different pinch-off region.

A semiconductor device is provided having a first region and a second region surrounding the first region includes a first electrode, a second electrode, a first semiconductor layer of a first conductivity type between the first electrode and the second electrode, a second semiconductor layer of the first conductivity type located over the first semiconductor layer, a third semiconductor layer of the second conductivity type on the second semiconductor layer in the first region, a fourth semiconductor layer of the first conductivity type between the third semiconductor layer and the second semiconductor layer, a fifth semiconductor layer of the second conductivity type on the second semiconductor layer in the second region, and a sixth semiconductor layer of the first conductivity type located between the fifth semiconductor layer and the second semiconductor layer, wherein the width of the fourth semiconductor layer is less than the width of the sixth semiconductor layer.