A vertical field effect transistor. The vertical field effect transistor includes: a drift area; a semiconductor fin on or above the drift area; a connection area on or above the semiconductor fin; and a gate electrode, which is formed adjacent to at least one side wall of the semiconductor fin, the semiconductor fin, in a first section, which is situated laterally adjacent to the gate electrode, having a lesser lateral extension than in a second section, which contacts the drift area, and/or than in a third section, which contacts the connection area.

A semiconductor device and a method of manufacturing the semiconductor device to achieve both of a high breakdown voltage and a low on resistance are provided. A semiconductor substrate includes a convex portion protruding upward from a surface of the semiconductor substrate. An n-type drift region is arranged on the semiconductor substrate so as to be positioned between a gate electrode and an n.sup.+-type drain region in plan view, and has an impurity concentration lower than an impurity concentration of the n.sup.+-type drain region. A p-type resurf region is arranged in the convex portion and forms a pn junction with the n-type drift region.

Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.

Disclosed is a high voltage semiconductor device and a method of manufacturing the same and, more particularly, to a high voltage semiconductor device and a method of manufacturing the same that enables an improvement in the breakdown voltage relative to the on-resistance by forming a top region in or at the surface of the substrate when the device includes a field plate adjacent to a gate electrode.

A semiconductor device according to an embodiment includes first and second electrode, and semiconductor layer between the first and the second electrode. The semiconductor layer has first and second plane. The semiconductor layer includes first region of first conductivity type, second region of second conductivity type between the first plane and the first region, third region of second conductivity type between the first plane and the first region and, fourth region of second conductivity type between the second and the third region, and fifth region of first conductivity type having first portion provided between the first and the fourth region. Width of the fourth region is larger than that of the second region. Distance between the second region and the first portion is smaller than distance between the second and the fourth region. And width of the first portion is smaller than that of the fourth region.

According to an embodiment, a transistor device includes a semiconductor body. The semiconductor body has a first surface, a second surface opposing the first surface, side faces, an active area, an edge termination region that laterally surrounds the active area, a drain region of a first conductivity type at the second surface, a drift region of the first conductivity type on the drain region, and a body region of a second conductivity type that opposes the first conductivity type on the drift region. In the active area, a source region of the first conductivity type is arranged on the body region. The body region has a doping concentration that is higher in the active area than in the edge termination region.

A semiconductor device according to an embodiment includes a first trench, a first gate electrode in the first trench, a second trench, a second gate electrode provided in the second trench, a third trench, a third gate electrode in the third trench, a first electrode pad electrically connected to the first gate electrode, a second electrode pad electrically connected to the second gate electrode, and a third electrode pad electrically connected to the third gate electrode, in which a thickness of a conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive semiconductor region opposed to the first gate electrode, and in which the thickness of the conductive semiconductor region opposed to the third gate electrode is smaller than a thickness of a conductive type semiconductor region opposed to the second gate electrode.

A lateral power semiconductor device includes a first type doping substrate at a bottom of the lateral power semiconductor device, a second type doping drift region, a second type heavy doping drain, a first type doping body; a first type heavy doping body contact and a second type heavy doping source, where dielectric layers are on a right side of the second type heavy doping source; the dielectric layers are arranged at intervals in a longitudinal direction in the first type doping body, and between adjacent dielectric layers in the longitudinal direction is the first type doping body; and a polysilicon is surrounded by the dielectric layer at least on a right side. Compared with conventional trench devices, the lateral power semiconductor device introduces a lateral channel, to increase a current density, thereby realizing a smaller channel on-resistance.

A semiconductor device of embodiments includes: a first silicon carbide region of first conductive type including a first region in contact with a first face of a silicon carbide layer having first and second faces; a second silicon carbide region of second conductive type above the first silicon carbide region; a third silicon carbide region of second conductive type above the second silicon carbide region; a fourth silicon carbide region of first conductive type above the second silicon carbide region; a first gate electrode and a second gate electrode extending in the first direction; a first electrode on the first face and including a first portion and a second portion between the first and the second gate electrode. The first portion contacts the third and the fourth silicon carbide region. The second portion provided in the first direction of the first portion and contacts with the first region.

A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.