A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

Some embodiments include an integrated assembly having an active region which contains semiconductor material. The active region includes first, second and third source/drain regions within the semiconductor material, includes a first channel region within the semiconductor material and between the first and second source/drain regions, and includes a second channel region within the semiconductor material and between the second and third source/drain regions. The semiconductor material includes at least one element selected from Group 13 of the periodic table. A digit line is electrically coupled with the second source/drain region. A first transistor gate is operatively proximate the first channel region. A second transistor gate is operatively proximate the second channel region. A first storage-element is electrically coupled with the first source/drain region. A second storage-element is electrically coupled with the third source/drain region. Some embodiments include methods of forming integrated assemblies.

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

A semiconductor device includes a core insulating layer extending in a first direction, an etch stop layer disposed on the core insulating layer, a channel layer extending along a sidewall of the core insulating layer and a sidewall of the etch stop layer, conductive patterns each surrounding the channel layer and stacked to be spaced apart from each other in the first direction, and an impurity region formed in an upper end of the channel layer.

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a stacked body including interlayer insulating layers and a select line disposed between the interlayer insulating layers, a core insulating layer penetrating the stacked body, a semiconductor pattern extending along a sidewall of the core insulating layer and including an undoped area disposed between the select line and the core insulating layer, doped semiconductor patterns disposed between the semiconductor pattern and the interlayer insulating layers, and a gate insulating layer disposed between the semiconductor pattern and the select line.

Provided are a semiconductor device, a method of manufacturing the semiconductor device, and an electronic apparatus including the semiconductor device. According to the embodiments, the semiconductor device may include: a vertical structure extending in a vertical direction relative to a substrate; and a nanosheet extending from the vertical structure and spaced apart from the substrate in the vertical direction, wherein the nanosheet includes a first portion in a first orientation, and at least one of an upper surface and a lower surface of the first portion is not parallel to a horizontal surface of the substrate.

A semiconductor structure includes: a substrate; bit lines located in the substrate and including a main body and a plurality of contact portions, the main body extending in a first direction, the contact portions being connected to the main body and extending toward the top surface of the substrate, and the plurality of contact portions being arranged at intervals in the first direction; and transistors located on a top surface of the contact portion, the extension direction of a channel of the transistor being perpendicular to a plane where the substrate is located.

A semiconductor device includes a substrate, a gate structure, a source region, a drain region, a doped region, and a channel region. The gate structure is disposed in the substrate, and the source region and drain regions being a first conductivity type respectively disposed at two sides of the gate structure. The doped region being a second conductivity type different from the first conductivity type is disposed below and separated from the gate structure, the source region, and drain region, the doped region. The channel region is disposed between the doped region and the gate structure and in contact with the doped region, and a dopant concentration of the channel region is less than a dopant concentration of the doped region.

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a substrate and a quantum well stack disposed on the substrate. The quantum well stack may include a quantum well layer and a back gate, and the back gate may be disposed between the quantum well layer and the substrate.