A semiconductor device with C-shaped channel portion and an electronic apparatus including the semiconductor device are disclosed. According to the embodiments, the semiconductor device may include a first semiconductor element and a second semiconductor element adjacent in a first direction. The first semiconductor element and the second semiconductor element may respectively include: a channel portion on a substrate, the channel portion including a curved nano-sheet or nano-wire with a C-shaped section; source/drain portions at upper and lower ends of the channel portion with respect to the substrate, respectively; and a gate stack surrounding a periphery of the channel portion. The channel portion of the first semiconductor element and the channel portion of the second semiconductor element may be substantially coplanar.

A method of manufacturing an integrated circuit device includes: doping a substrate with a first type dopant to form a well region; forming a first semiconductor fin and a second semiconductor fin wider than the first semiconductor fin over the well region; forming a first source/drain region of a second type dopant on the first semiconductor fin, the second type dopant is of a different conductivity type than the first type dopant; forming a second source/drain region of the first type dopant on the second semiconductor fin.

Provided are a layer structure including a configuration capable of increasing the operation characteristics of a device including the layer structure, a method of manufacturing the layer structure, an electronic device including the layer structure, and an electronic apparatus including the electronic device. The layer structure includes a first layer and a second layer on one surface of the first layer and facing the first layer. The first layer and the second layer overlap each other. One layer of the first layer and the second layer has a trace of applied strain, and an other layer of the first layer and the second layer is a strain-inducing layer that applies a strain to the one layer.

Some embodiments include a pillar which contains semiconductor material, and which extends primarily along a first direction. A cross-section through the pillar along a second direction orthogonal to the first direction is through the semiconductor material and includes a lateral periphery of the pillar configured as three-sided shape. Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the vertical stack. Each of the channel-material-pillars has a top-down cross-section which includes a lateral periphery configured as three-sided shape of an equilateral triangle with rounded vertices.

The present disclosure relates to a FinFET structure and a method of manufacturing the same. The FinFET structure includes a first fin and a second fin. The first fin is over a first base and has a first channel region. The first channel region has a first channel length. The second fin is over a second base and has a second channel region. The second channel region has a second channel length. The second channel length is different from the first channel length.

NOR memory strings may be used for implementations of logic functions involving many Boolean variables, or to generate analog signals whose magnitudes are each representative of the bit values of many Boolean variables. The advantage of using NOR memory strings in these manners is that the logic function or analog signal generation may be accomplished within one simultaneous read operation on the NOR memory strings.

A semiconductor device includes a first device disposed in an NMOS region of the semiconductor device. The first device includes a first gate-all-around (GAA) device having a vertical stack of nano-structure channels. The semiconductor device also includes a second device in a PMOS region of the semiconductor device. The second device includes a FinFET that includes a fin structure having a fin width. The fin structure is separated from an adjacent fin structure by a fin pitch. A maximum channel width of the nano-structure channels is no greater than a sum of: the fin width and the fin pitch. Alternatively, the second device includes a second GAA device having a different number of nano-structure channels than the first GAA device.

In some embodiments, the present disclosure relates to an integrated chip that includes a first nanosheet field effect transistor (NSFET). The first NSFET includes a first nanosheet channel structure arranged over a substrate, a second nanosheet channel structure arranged directly over the first nanosheet channel structure, and a first gate electrode structure. The first and second nanosheet channel structures extend in parallel between first and second source/drain regions. The first gate electrode structure includes a first conductive ring and a second conductive ring that completely surround outer sidewalls of the first nanosheet channel structure and the second nanosheet channel structure, respectively, and that comprise a first material. The first gate electrode structure also includes a passivation layer that completely surrounds the first and second conductive rings, is arranged directly between the first and second nanosheet channel structures, and comprises a second material different than the first material.

Thin film transistors having fin structures integrated with two-dimensional (2D) channel materials are described. In an example, an integrated circuit structure includes a plurality of insulator fins above a substrate. A two-dimensional (2D) material layer is over the plurality of insulator fins. A gate dielectric layer is on the 2D material layer. A gate electrode is on the gate dielectric layer. A first conductive contact is on the 2D material layer adjacent to a first side of the gate electrode. A second conductive contact is on the 2D material layer adjacent to a second side of the gate electrode, the second side opposite the first side.

A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.