A transistor structure can include a semiconductor-on-insulator substrate that includes an upper substrate region separated from a lower substrate region by a buried insulator. Shallow halo implant regions can be formed in an upper substrate region having a peak concentration at a first depth within the upper substrate region. Deep halo implant regions can be formed in the upper substrate region having a peak concentration at a second depth lower than the first depth. An epitaxial layer can be formed on top of the upper substrate region and below the control gate. Source and drain regions both of a second conductivity type formed in at least the epitaxial layer. In some embodiments, a lower substrate region can be biased for a double-gate effect.

A semiconductor device of embodiments includes: a silicon carbide layer including a trench, a n-type first SiC region, a p-type second SiC region on the first SiC region, a n-type third SiC region on the second SiC region, a fourth SiC region of p-type between the first trench and the first SiC region, and a fifth SiC region electrically connecting the second SiC region and the fourth SiC region; and a gate electrode in the trench. The first trench has a first region extending in a first direction, a second region continuous with the first region, and a third region continuous with the second region and extending in the first direction. The second width of the second region in the second direction is larger than the first width of the first region in the second direction. The fifth SiC region is disposed in the second direction of the second region.

In an embodiment, an integrated circuit (IC) device comprises a semiconductor substrate, an isolation region and an active region disposed on the semiconductor substrate, a gate stack disposed over the active region, and a source and a drain disposed in the active region and interposed by the gate stack in a first direction. The active region is at least partially surrounded by the isolation region. A middle portion of the active region laterally extends beyond the gate stack in a second direction that is perpendicular to the first direction.

A method for forming a semiconductor structure includes: providing a substrate, in which a gate structure is formed on the substrate; forming first side walls covering side surfaces of the gate structure, in which the first side walls have a first preset thickness in a direction parallel to a plane of the substrate; performing first ion implantation on the substrate on both sides of the gate structure exposed to the first side walls; removing a part of the first side walls to form second side walls, in which the second side walls have a second preset thickness in the direction parallel to the plane of the substrate; and performing second ion implantation on the substrate on both sides of the gate structure, in which doping types of the first ion implantation and the second ion implantation are different.

A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.

FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function Φ.sub.MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function Φ.sub.MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

The present disclosure provides a method of manufacturing a semiconductor device. The method includes steps of providing a patterned mask having a plurality of openings on a substrate; etching the substrate through the openings to form an etched substrate and a trench in the etched substrate, wherein the etched substrate comprises a protrusion; introducing dopants having a first conductivity type in the etched substrate and on either side of the trench to form a plurality of first impurity regions; forming an isolation film in the trench; and depositing a conductive material on the isolation film.

A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on the second electrode portion, the first electrode portion being provided between the first trench and the second trench, the first electrode portion reaching the first semiconductor region from above the second semiconductor region, the first electrode portion being electrically connected to the first semiconductor region and the second semiconductor region; a third semiconductor region provided between the third electrode and the second semiconductor region provided between the first insulating film and the third electrode, the third semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; a fourth semiconductor region provided between the third electrode and the second semiconductor region provided between the second insulating film and the third electrode, the fourth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; and a fifth semiconductor region provided between the first semiconductor region and the third electrode, the fifth semiconductor region being provided apart from the third semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region.

A semiconductor device includes: a first semiconductor layer of first conductivity type; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of first conductivity type provided on the first semiconductor region; a first electrode provided in a first trench, the first trench reaching the second semiconductor layer from above the first semiconductor region, the first electrode facing the first semiconductor region via a first insulating film; a second electrode provided in a second trench, the second trench reaching the second semiconductor layer from above the first semiconductor region, the second electrode facing the first semiconductor region via a second insulating film; a third electrode including a first electrode portion, a second electrode portion provided on the first electrode portion and a third electrode portion provided on the second electrode portion, the first electrode portion being provided between the first trench and the second trench, the first electrode portion reaching the first semiconductor region from above the second semiconductor region, the first electrode portion being electrically connected to the first semiconductor region and the second semiconductor region; a third semiconductor region provided between the third electrode and the second semiconductor region provided between the first insulating film and the third electrode, the third semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; a fourth semiconductor region provided between the third electrode and the second semiconductor region provided between the second insulating film and the third electrode, the fourth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region; and a fifth semiconductor region provided between the first semiconductor region and the third electrode, the fifth semiconductor region being provided apart from the third semiconductor region and the fourth semiconductor region, the fifth semiconductor region having a higher concentration of impurities of second conductivity type than the first semiconductor region.

A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region, including forming a doped region on a substrate, forming one or more interfacial features on the doped region, and forming a source/drain contact on at least a portion of the doped region, wherein the one or more interfacial features increases the surface area of the interface between the source/drain contact and the doped region compared to a flat source/drain contact-doped region interface.