A semiconductor device includes a substrate, a first well region in the substrate, a gate structure over the substrate, a second well region and a third well region in the substrate and under the gate structure, and a source region and a drain region on opposite sides of the gate structure. The drain region is in the second well region and the source region is in the third well region. The drain region has a first doped region and a second doped region, and the first doped region and the second doped region have different conductivity types.

A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.

A method for manufacturing a semiconductor device includes forming a source and region in a substrate. A core channel region is formed adjacent the source region. A barrier layer is formed adjacent the core channel region. A drain region is formed in the substrate such that the barrier layer is between the core channel region and the drain region. A first portion of a shell is formed along the core channel region. A second portion of the shell is formed along the barrier layer. The second portion of the shell includes a different material than the first portion of the shell.

A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.

A method is provided for fabricating an LDMOS transistor. The method includes providing a base substrate. The method also includes forming a first well area doped with a first well ion in the base substrate. In addition, the method includes forming a second well area doped with a second well ion in the base substrate, where the second well area includes a first region adjacent to the first well area. Moreover, the method includes forming a first ion doping region doped with first ions in the first well area and the first region, where a type of the first ions is the same as a type of the first well ion and opposite to a type of the second well ion. Further, the method includes forming a gate structure on part of the first well area and part of the first region.

A solid-state imaging device includes a first pixel and a second pixel. The first pixel includes a light-shielding part having an opening of a predetermined size. The second pixel includes a light-shielding part having an opening of the predetermined size at a position different from a position of the opening of the first pixel.

A metal oxide semiconductor field effect transistor (MOSFET), a method for manufacturing MOSFET, and an electronic apparatus including MOSFET are disclosed. The MOSFET include: a vertical channel portion on a substrate; source/drain portions respectively located at upper and lower ends of the channel portion with respect to the substrate; and a gate stack opposite to the channel portion. The channel portion has doping concentration distribution, so that when the MOSFET is an n-type MOSFET (nMOSFET), a threshold voltage of a first portion of the channel portion close to one of the source/drain portions is lower than a threshold voltage of a second portion adjacent to the first portion; or when the MOSFET is a p-type MOSFET (pMOSFET), a threshold voltage of a first portion in the channel portion close to one of the source/drain portions is higher than a threshold voltage of a second portion adjacent to the first portion.

The present disclosure provides a metal oxide semiconductor device and a method for manufacturing the same. The metal oxide semiconductor device includes a semiconductor substrate, a patterned field oxide layer, first JFET implantation regions and second JFET implantation regions. Active regions and gate regions are formed on an upper surface of the semiconductor substrate, each active region is surrounded by two or more of the gate regions, and the gate regions form a grid and some gate regions overlap to form gate intersections. The first JFET implantation regions are formed by implanting ions underneath the gate intersections of the upper surface of the semiconductor substrate. Orthogonal projections of the first JFET implantation regions and the field oxide layer onto the substrate don't overlap. The second JFET implantation regions are formed by implanting ions into the upper surface of the semiconductor substrate and located underneath the gate regions that are not gate intersections.