A semiconductor device includes a silicon semiconductor body having a main surface and a nitrogen concentration which is lower than about 2*10.sup.14 cm.sup.−3 at least in a first portion of the silicon semiconductor body, the first portion extending from the main surface to a depth of about 50 μm. The nitrogen concentration increases with a distance from the main surface at least in the first portion. The semiconductor device further includes a field-effect structure arranged next to the main surface.

A semiconductor device having a semiconductor substrate that includes a first-conductivity-type substrate and a first-conductivity-type epitaxial layer, and a plurality of trenches reaching a predetermined depth from a main surface of the semiconductor substrate to terminate in the first-conductivity-type epitaxial layer. The semiconductor substrate includes a hydrogen-donor introduced part, of which a concentration of a hydrogen donor is greatest at a depth position that is separate from bottoms of the trenches by a distance at least two times of the depth of the trenches. The impurity concentration of an impurity dopant of the first-conductivity-type substrate being lower than that of the first-conductivity-type epitaxial layer. A difference between a first resistivity, corresponding to a total impurity concentration of the impurity dopant and the hydrogen donor of the first-conductivity-type substrate, and a second resistivity, corresponding to the impurity concentration of the impurity dopant of the first-conductivity-type epitaxial layer, is at most 20%.

A semiconductor device includes a first fin pattern, which includes a first lower pattern and a first upper pattern stacked sequentially on a substrate, the first upper pattern including a first part and second parts respectively disposed on both sides of the first part, a gate electrode, which is formed on the first part to intersect the first fin pattern, and source/drain regions, which are formed on the second parts, respectively. A dopant concentration of the first upper pattern is higher than a dopant concentration of the first lower pattern and a dopant concentration of the substrate, and the dopant concentration of the first lower pattern is different from the dopant concentration of the substrate.

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

A method of forming a transistor can include forming a gate mask on a substrate having a vertical location aligned with that of a transistor control gate; implanting first conductivity type dopants with the gate mask as an implant mask to form a first shallow halo region; implanting first conductivity type dopants with at least the gate mask as an implant mask to form a first deep halo region having a peak dopant concentration profile at a greater substrate depth than the first shallow halo region; forming an epitaxial layer on top of the substrate; forming a first control gate structure on the epitaxial layer; and forming a first source or drain region, of a second conductivity type, in at least the epitaxial layer to a side of the first control gate, and over the first shallow halo region and the first deep halo region.

An integrated circuit having field effect transistors and manufacturing method. One embodiment provides an integrated circuit including a first FET and a second FET. At least one of source, drain, gate of the first FET is electrically connected to the corresponding one of source, drain, gate of the second FET. At least one further of source, drain, gate of the first FET and the corresponding one further of source, drain, gate of the second FET are connected to a circuit element, respectively. A dopant concentration of a body along a channel of each of the first and second FETs has a peak at a peak location within the channel.

A solar cell includes: a semiconductor substrate which includes a first principal surface and a second principal surface; a first semiconductor layer of the first conductivity type disposed above the first principal surface; and a second semiconductor layer of a second conductivity type disposed below the second principal surface. The semiconductor substrate includes: a first impurity region of the first conductivity type; a second impurity region of the first conductivity type disposed between the first impurity region and the first semiconductor layer; and a third impurity region of the first conductivity type disposed between the first impurity region and the second semiconductor layer. A concentration of an impurity in the second impurity region is higher than a concentration of the impurity in the third impurity region, and the concentration of the impurity in the third impurity region is higher than a concentration of the impurity in the first impurity region.

A switching element includes a semiconductor substrate having: an n-type drift region in contact with each of gate insulating films on a bottom surface and side surfaces of each of the trenches; a p-type body region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the n-type drift region; an n-type source region in contact with the gate insulating films on the side surfaces of each of the trenches at a position above the p-type body region, the n-type source region being separated away from the n-type drift region by the p-type body region; plurality of p-type bottom regions each of which is located under a corresponding one of the trenches and located away from a corresponding one of the gate insulating films; and a p-type connection region that connects the p-type bottom regions and the p-type body region.

The present technology relates to an imaging element, an imaging device, and a manufacturing apparatus and a method that facilitate electric charge transfer. An imaging element of the present technology includes a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. Also, an imaging device of the present technology includes: an imaging element including a vertical transistor that has a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit; and an image processing unit that performs image processing on captured image data obtained by the imaging element. Further, a manufacturing apparatus of the present technology includes a vertical transistor manufacturing unit that manufactures a vertical transistor having a potential with a gradient in at least part of a charge transfer channel that transfers electric charge of a photoelectric conversion unit. The present technology can be applied to imaging elements, imaging devices, and manufacturing apparatuses and methods, for example.