A double Schottky-barrier diode includes a semi-insulating substrate, a left mesa formed by growth and etching on the semi-insulating substrate, a middle mesa formed by growth and etching on the semi-insulating substrate, a right mesa formed by growth and etching on the semi-insulating substrate, two anode probes and two air-bridge fingers. The two Schottky contacts are closely fabricated on the same mesa (middle mesa) in a back-to-back manner to obtain even symmetric C-V characteristics and odd symmetric I-V characteristics from the device level. The output of a frequency multiplier fabricated using the double Schottky-barrier diode only has odd harmonics, but no even harmonics, which is suitable for the production of high-order frequency multipliers. The cathodes of the two Schottky contacts are connected by the buffer layer without ohmic contact.

A Schottky diode comprises: a first electrode; a second electrode; and a body of semiconductive material connected to the first electrode at a first interface and connected to the second electrode at a second interface, wherein the first interface comprises a first planar region lying in a first plane and the first electrode has a first projection onto the first plane in a first direction normal to the first plane, the second interface comprises a second planar region lying in a second plane and the second electrode has a second projection onto the first plane in said first direction, at least a portion of the second projection lies outside the first projection, said second planar region is offset from the first planar region in said first direction, and one of the first interface and the second interface provides a Schottky contact.

A nitride semiconductor laminate includes: a substrate comprising a group III nitride semiconductor and including a surface and a reverse surface, the surface being formed from a nitrogen-polar surface, the reverse surface being formed from a group III element-polar surface and being provided on the reverse side from the surface; a protective layer provided at least on the reverse surface side of the substrate and having higher heat resistance than the reverse surface of the substrate; and a semiconductor layer provided on the surface side of the substrate and comprising a group III nitride semiconductor. The concentration of O in the semiconductor layer is lower than 1×10.sup.17 at/cm.sup.3.

A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.

Disclosed are a Schottky diode and a manufacturing method thereof. The Schottky diode includes a substrate, a first semiconductor layer, a heterostructure layer, and a passivation layer, where the passivation layer includes a first groove and a second groove, and the first groove and the second groove penetrate the passivation layer and expose the heterostructure layer; a second semiconductor layer, where the second semiconductor layer is located in the first groove, and the second semiconductor layer does not fully fill the first groove in a horizontal direction; a first electrode, where the first electrode is at least located on a heterostructure layer and the second semiconductor layer that are corresponding to the first groove; and a second electrode located in the second groove.

The present disclosure relates to a wide band-gap merged p-i-n/Schottky, MPS, diode, and to a method of manufacturing the same. The present disclosure particularly relates to Silicon Carbide, SiC, MPS diodes. According to the present disclosure, the MPS diode includes different Schottky contacts with different IV characteristics, and/or ohmic contacts with a different contact resistance and/or threshold voltage. This allows the conduction area of the MPS diode to change more gradually with forward bias thereby avoiding drawbacks associated with a large conduction area when switching from a forward biasing mode to a reverse biasing mode. Therefore, the dynamic switching performance can be improved in a wide operation voltage range.

Disclosed herein are IC devices, packages, and device assemblies that include III-N diodes with n-doped wells and capping layers. An example IC device includes a support structure and a III-N layer, provided over a portion of the support structure, the III-N layer including an n-doped well of a III-N semiconductor material having n-type dopants with a dopant concentration of at least 5×10.sup.17 dopants per cubic centimeter. The IC device further includes a first and a second electrodes and at least one capping layer. The first electrode interfaces a first portion of the n-doped well. The capping layer interfaces a second portion of the n-doped well and includes a semiconductor material with a dopant concentration below 10.sup.17 dopants per cubic centimeter. The second electrode is provided so that the capping layer is between the second portion of the n-doped well and the second electrode.

The present disclosure provides a semiconductor device, a manufacturing method, and electronic equipment. The semiconductor device comprising: a substrate; an interface, for generating two-dimensional charge carrier gas; a first electrode and a second electrode; and a first semiconductor layer of a first type doping formed on the substrate, wherein first regions and a second region are formed in the first semiconductor layer, wherein in the first regions, the dopant atoms of the first type do not have electrical activity, and in the second region, the dopant atoms of the first type have electrical activity; and the second region comprises a portion coplanar with the first regions. The semiconductor device can not only avoid damage to the crystal structure, but also can be easily realized in the processing, and it can maintain good transport properties of the two-dimensional charge carrier gas, which is beneficial to the improvement of device performance.

A junction barrier Schottky diode device and a method for fabricating the same is disclosed. In the junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

The present disclosure relates to a semiconductor device and a manufacturing method thereof; wherein the semiconductor device comprises a semiconductor device layer including one or more semiconductor devices; a first electrode interconnection layer disposed on a first side of the semiconductor device layer; one or more first metal pillars disposed on the first side of the semiconductor device layer and electrically connected to the first electrode interconnection layer; a first insulating material disposed around the one or more first metal pillars, wherein the first insulating material is an injection molding material; and a second electrode interconnection layer disposed on a second side opposite to the first side of the semiconductor device layer. In the technical scheme of the present disclosure, the temporary substrate is not required to achieve better support strength and complete the related processes of the semiconductor manufacturing process, which is convenient, convenient and low in cost.