A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.

The vertical-conduction electronic power device is formed by a body of wide band gap semiconductor which has a first conductivity type and has a surface, and is formed by a drift region and by a plurality of surface portions delimited by the surface. The electronic device is further formed by a plurality of first implanted regions having a second conductivity type, which extend into the drift region from the surface, and by a plurality of metal portions, which are arranged on the surface. Each metal portion is in Schottky contact with a respective surface portion of the plurality of surface portions so as to form a plurality of Schottky diodes formed by first Schottky diodes and second Schottky diodes, wherein the first Schottky diodes have, at equilibrium, a Schottky barrier having a height different from that of the second Schottky diodes.

A method of fabricating a power semiconductor device includes forming a bi layer mask on a semiconductor substrate, where the bilayer mask comprises a first dielectric layer on the semiconductor substrate and a second dielectric layer on the first dielectric layer. The first and second dielectric layers are through-etched to define an exposed portion of the semiconductor substrate. The first dielectric layer is selectively etched to form an undercut region of the bi layer mask. A crystalline semiconductor material is epitaxially grown on the exposed portion of the semiconductor substrate, and a polycrystalline semiconductor material is deposited on the second dielectric layer of the bilayer mask. After the epitaxial growth, the bilayer mask and the polycrystalline semiconductor material are removed from the semiconductor substrate, leaving behind a mesa comprising the crystalline semiconductor material on the semiconductor substrate. Advantageously, a sidewall of the mesa is substantially smooth and/or defect-free.

An electron extraction type free-wheeling diode device and a preparation method thereof are provided by the present disclosure, and more than one first structures for increasing the density of electron extraction pathways are provided on a N-type drift region. Each of the first structures includes a lightly doped P-type base region, a heavily doped N-type emitter region located on the lightly doped P-type base region, a P-type trench anode region, and a trench region located on the P-type trench anode region. The barrier height of the punch-through NPN triode can be tuned in a wide range, which has beneficial effects on soft and fast adjustment of the reverse recovery process.

A process of forming an electronic device can form an accumulation channel or an integrated diode by selective doping parts of a workpiece. In an embodiment, a doped region can be formed by implanting a sidewall of a body region. In another embodiment, a doped region can correspond to a remaining portion of a semiconductor layer after forming another doped region by implanting into a contact opening. The accumulation channel or the integrated diode can lower the barrier for a body diode turn-on. Reduced stored charge and Q.sub.RR may be achieved, leading to lower switching losses.

A semiconductor device includes a first substrate having opposite first and second sides, a first conductive layer on the first side of the first substrate, and a second substrate having opposite first and second sides. The second side of the second substrate is bonded to the first side of the first substrate. The second substrate includes a semiconductor material, and at least one circuit element electrically coupled to the first conductive layer. The at least one circuit element includes at least one of a Schottky diode configured by the semiconductor material and a first contact structure, a capacitor having a first electrode of the semiconductor material, or a resistor of the semiconductor material.

A monolithic component includes a field-effect power transistor and at least one first Schottky diode inside and on top of a gallium nitride substrate.

A group III nitride transistor structure capable of reducing a leakage current and a fabricating method thereof are provided. The group III nitride transistor structure includes: a first heterojunction and a second heterojunction which are laminated, wherein the first heterojunction is electrically isolated from the second heterojunction via a high resistance material and/or insertion layer; a first electrode, a second electrode and a first gate which are matched with the first heterojunction, wherein a third semiconductor is arranged between the first gate and the first heterojunction, and the first gate is also electrically connected with the first electrode; a source, a drain and a second gate which are matched with the second heterojunction, wherein the source and the drain are also respectively electrically connected with the first gate and the second electrode, and a sixth semiconductor is arranged between the second gate and the second heterojunction.

The present disclosure relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a first channel layer; a first barrier layer, wherein a first heterojunction having a vertical interface is formed between the first channel layer and the first barrier layer, and a vertical 2DEG or 2DHG is formed in the first heterojunction; a first electrode positioned on an upper side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the first electrode is connected to a first external voltage above the first heterojunction; and a second electrode positioned at a lower side of the first heterojunction and configured to make electrical contact with 2DEG or 2DHG within the first heterojunction, wherein the second electrode is connected to a second external voltage below the first heterojunction. The semiconductor device of the present disclosure can not only is improve the withstand voltage of the device, but also facilitate the circuit interconnection of the semiconductor device.

A method for fabricating a junction barrier Schottky diode device is disclosed. The junction barrier Schottky device includes an N-type semiconductor layer, a plurality of first P-type doped areas, a plurality of second P-type doped areas, and a conductive metal layer. The first P-type doped areas and the second P-type doped are formed in the N-type semiconductor layer. The second P-type doped areas are self-alignedly formed above the first P-type doped areas. The spacing between every neighboring two of the second P-type doped areas is larger than the spacing between every neighboring two of the first P-type doped areas. The conductive metal layer, formed on the N-type semiconductor layer, covers the first P-type doped areas and the second P-type doped areas.