A nitride semiconductor device 1 includes a first transistor 3 which is constituted of a normally-off transistor and functions as a main transistor and a second transistor 4 which is constituted of a normally-on transistor and arranged to limit a gate current of the first transistor. The first transistor 3 includes a first electron transit layer 7A constituted of a nitride semiconductor and a first electron supply layer 8A which is formed on the first electron transit layer and constituted of a nitride semiconductor. The second transistor 4 includes a second electron transit layer 7B constituted of a nitride semiconductor and a second electron supply layer 8B which is formed on the second electron transit layer and constituted of a nitride semiconductor. A gate electrode 51 and a source electrode 44 of the second transistor 4 are electrically connected to a gate electrode 16 of the first transistor 3.

A MOSFET with saturation contact. The MOSFET with saturation contact includes an n-doped source region, a source contact, a contact structure, which extends from the source contact to the n-doped source region, and forms with the source contact a first conductive connection and forms with the n-doped source region a second conductive connection, a barrier layer and an insulating layer. The contact structure includes a section between the first conductive connection and the second conductive connection, which is embedded between the barrier layer and the dielectric layer and is configured in such a way that a two-dimensional electron gas is formed therein.

The on-resistance of each of field effect transistors having different planar sizes is reduced. A semiconductor device includes first and second field effect transistors mounted on a semiconductor substrate and an insulating layer provided on a main surface of the semiconductor substrate. Here, each of the first and second field effect transistors includes a pair of main electrodes which are separated from each other and provided on the main surface of the semiconductor substrate, a cavity part which is provided in the insulating layer between the pair of main electrodes, and a gate electrode which has a head part positioned on the insulating layer and a body part that penetrates the insulating layer from the head part and protrudes toward the cavity part and in which the head part is wider than the body part. Here, the width of the cavity part of the second field effect transistor is different from the width of the cavity part of the first field effect transistor.

Provided are a semi-conductor structure and a manufacturing method thereof. The semi-conductor structure includes: a substrate, a heterojunction, a P-type ion doped layer and a gate insulation layer disposed from bottom to top, wherein the heterojunction includes a source region, a drain region and a gate region; the P-type ion doped layer in the gate region includes an activated region and non-activated regions, P-type doping ions in the activated region are activated, and P-type doping ions in the non-activated regions are passivated; the non-activated regions include at least two regions which are spaced apart in a direction perpendicular to a connection line of the source region and the drain region; the gate insulation layer is located on the non-activated region to expose the activated region.

Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.

A high electron mobility transistor (HEMT) includes a carrier transit layer, a carrier supply layer, a main gate, a control gate, a source electrode and a drain electrode. The carrier transit layer is on a substrate. The carrier supply layer is on the carrier transit layer. The main gate and the control gate are on the carrier supply layer. A fluoride ion doped region is formed right below the main gate in the carrier supply layer. The source electrode and the drain electrode are at two opposite sides of the main gate and the control gate, wherein the source electrode is electrically connected to the control gate by a metal interconnect. The present invention also provides a method of forming a high electron mobility transistor (HEMT).

A semiconductor device includes a III-V compound semiconductor layer, a III-V compound barrier layer, a gate trench, and a p-type doped III-V compound layer. The III-V compound barrier layer is disposed on the III-V compound semiconductor layer. The gate trench is disposed in the III-V compound barrier layer. The p-type doped III-V compound layer is disposed in the gate trench, and a top surface of the p-type doped III-V compound layer and a top surface of the III-V compound barrier layer are substantially coplanar.

A resistor-transistor-logic circuit with GaN structures, including a 2DEG resistor having a drain connected with an operating voltage, and a logic FET having a gate connected to an input voltage, a source grounded and a drain connected with a source of the 2DEG resistor and connected collectively to an output voltage.

A multi-finger high-electron mobility transistor and a method of manufacturing such a transistor, and an electronic device including such a transistor is provided. According to an aspect of the present disclosure, an etching step for reducing donor layer thickness and/or performing an ion implantation is used for locally reducing the 2DEG concentration.

Structures including a compound-semiconductor-based device and a silicon-based device integrated on a semiconductor substrate and methods of forming such structures. The structure includes a first semiconductor layer having a top surface and a faceted surface that fully surrounds the top surface. The top surface has a first surface normal, and the faceted surface has a second surface normal that is inclined relative to the first surface normal. A layer stack that includes second semiconductor layers is positioned on the faceted surface of the first semiconductor layer. Each of the second semiconductor layers contains a compound semiconductor material. A silicon-based device is located on the top surface of the first semiconductor layer, and a compound-semiconductor-based device is located on the layer stack.